3850 Group (Spec.A QzROM version) REJ03B0125-0210 Rev.2.10 Nov 14, 2005 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION The 3850 group (spec.A QzROM version) is the 8-bit microcomputer based on the 740 family core technology. The 3850 group (spec.A QzROM version) is designed for the household products and office automation equipment and includes serial interface functions, 8-bit timer, and A/D converter. FEATURES * Basic machine-language instructions ................................. 71 * Minimum instruction execution time .......................... 0.32 s (at 12.5 MHz oscillation frequency) * Memory size ROM ..................................................................... 16 K bytes RAM ........................................................................ 512 bytes * Programmable input/output ports ....................................... 34 * On-chip software pull-up resistor * Interrupts ............................................. 15 sources, 14 vectors * Timers ....................................................................... 8-bit x 4 * Serial interface Serial I/O1 ............. 8-bit x 1 (UART or Clock-synchronized) Serial I/O2 ............................. 8-bit x 1 (Clock-synchronized) * PWM ......................................................................... 8-bit x 1 * A/D converter .......................................... 10-bit x 9 channels * Watchdog timer ....................................................... 16-bit x 1 * Clock generating circuit ............................. Built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator) * Power source voltage [In high-speed mode] f(XIN) 12.5 MHz ............................................. 4.0 to 5.5 V f(XIN) 6.0 MHz ............................................... 2.7 to 5.5 V f(XIN) 4.2 MHz ............................................... 2.2 to 5.5 V f(XIN) 2.1 MHz ............................................... 2.0 to 5.5 V [In middle-speed mode] f(XIN) 12.5 MHz ............................................. 2.7 to 5.5 V f(XIN) 8.4 MHz ............................................... 2.2 to 5.5 V f(XIN) 4.2 MHz ............................................... 1.8 to 5.5 V [In low-speed mode] f(XCIN) 50 kHz................................................ 1.8 to 5.5 V * Power dissipation In high-speed mode ........................................... 30 mW (typ.) (at 12.5 MHz oscillation frequency, at 5 V power source voltage) In low-speed mode ............................................ 45 W (typ.) (at 32 kHz oscillation frequency, at 3 V power source voltage) * Operating temperature range ............................. -20 to 85 C APPLICATION Household products, Consumer electronics, etc. PIN CONFIGURATION (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 M38503G4A-XXXSP/FP M38503G4ASP/FP VCC VREF AVSS P44/INT3/PWM P43/INT2/SCMP2 P42/INT1 P41/INT0 P40/CNTR1 P27/CNTR0/SRDY1 P26/SCLK1 P25/TxD P24/RxD P23 P22 CNVSS P21/XCIN P20/XCOUT RESET XIN XOUT VSS 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P30/AN0 P31/AN1 P32/AN2 P33/AN3 P34/AN4 P00/SIN2 P01/SOUT2 P02/SCLK2 P03/SRDY2 P04/AN5 P05/AN6 P06/AN7 P07/AN8 P10(LED0) P11(LED1) P12(LED2) P13(LED3) P14(LED4) P15(LED5) P16(LED6) P17(LED7) Package type : FP........... 42P2R-A/E (42-pin plastic-molded SSOP) Package type : SP........... PRDP0042BA-A (42P4B) (42-pin plastic-molded SDIP) Fig 1. Pin configuration Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 1 of 59 Fig 2. Functional block diagram Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 2 of 59 Sub-clock input X CIN 3 AV SS V REF 2 A/D converter (10) PWM (8) Reset Sub-clock output X COUT Clock generating circuit 20 Main-clock output X OUT Watchdog timer 19 Main-clock input X IN FUNCTIONAL BLOCK DIAGRAM I/O port P3 I/O port P4 P3(5) 38 39 40 41 42 INT 0INT 3 ROM 4 5 6 7 8 P4(5) RAM 21 V SS PC H SI/O1 (8) C P U 1 V CC PS PC L S Y X A 18 RESET Reset input CNTR 0 P2(8) CNTR 1 I/O port P2 X COUT X CIN Prescaler Y (8) Prescaler X (8) Prescaler 12 (8) 9 10 11 12 13 1416 17 15 CNV SS I/O port P1 22 23 24 25 26 27 28 29 P1(8) Timer Y (8) Timer X (8) Timer 2 (8) Timer 1 (8) I/O port P0 30 31 32 33 34 35 36 37 P0(8) SI/O2 (8) 3850 Group (Spec.A QzROM version) 3850 Group (Spec.A QzROM version) PIN DESCRIPTION Table 1 Pin description Pin Name Function Function except a port function VCC, VSS Power source Apply voltage of 1.8 V-5.5 V to VCC, and 0 V to VSS. CNVSS CNVSS input * This pin controls the operation mode of the chip and is shared with the VPP pin which is the power source input pin for programming the built-in QzROM. * Normally connected to VSS. VREF Reference voltage Reference voltage input pin for A/D converter. AVSS Analog power source * Analog power source input pin for A/D converter. * Connect to VSS. RESET Reset input * Reset input pin for active "L". XIN Clock input XOUT Clock output * Input and output pins for the clock generating circuit. * Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. * When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. P00/SIN2 P01/SOUT2 P02/SCLK2 P03/SRDY2 I/O port P0 P04/AN5-P07/AN8 P10-P17 I/O port P1 P20/XCOUT P21/XCIN I/O port P2 P22 P23 P24/RXD P25/TXD P26/SCLK1 P27/CNTR0/SRDY1 * 8-bit CMOS I/O port. * I/O direction register allows each pin to be individually programmed as either input or output. * CMOS compatible input level. * CMOS 3-state output structure. * Pull-up control is enabled in a byte unit. * P10 to P17 (8 bits) are enabled to output large current for LED drive. * Serial I/O2 function pin * 8-bit CMOS I/O port. * I/O direction register allows each pin to be individually programmed as either input or output. * CMOS compatible input level. * P20, P21, P24, to P27: CMOS3-state output structure. * P22, P23: N-channel open-drain structure. * Pull-up control of P20, P21, P24-P27 is enabled in a byte unit. * Sub-clock generating circuit I/O pins (connect a resonator) * A/D converter input pin * Serial I/O1 function pin * Serial I/O1 function pin * Timer X function pin P30/AN0-P34/AN4 I/O port P3 * * * * 5-bit CMOS I/O port with the same function as port P0. * A/D converter input pin CMOS compatible input level. CMOS 3-state output structure. Pull-up control is enabled in a bit unit. P40/CNTR1 * * * * 5-bit CMOS I/O port with the same function as port P0. * Timer Y function pin CMOS compatible input level. * Interrupt input pins CMOS 3-state output structure. Pull-up control is enabled in a bit unit. * Interrupt input pin * SCMP2 output pin I/O port P4 P41/INT0 P42/INT1 P43/INT2/SCMP2 P44/INT3/PWM Rev.2.10 Nov 14, 2005 REJ03B0125-0210 * Interrupt input pin * PWM output pin Page 3 of 59 3850 Group (Spec.A QzROM version) PART NUMBERING Product name M3850 3 G 4 A- XXX SP Package type SP : PRDP0042BA-A FP : 42P2R-A/E ROM number Omitted in blank version. A- : High-speed version "-" is omitted in the shipped in blank version. QzROM memory size 1 : 4096 bytes 9 : 36864 bytes 2 : 8192 bytes A : 40960 bytes 3 : 12288 bytes B : 45056 bytes 4 : 16384 bytes C : 49152 bytes 5 : 20480 bytes D : 53248 bytes 6 : 24576 bytes E : 57344 bytes 7 : 28672 bytes F : 61440 bytes 8 : 32768 bytes The first 128 bytes and the last 2 bytes of RAM, and 1 byte of address FFDB16 are reserved areas; they cannot be used as a user's ROM area. Memory type G : QzROM version RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes Fig 3. Part numbering Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 4 of 59 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 8 : 1536 bytes 9 : 2048 bytes 3850 Group (Spec.A QzROM version) GROUP EXPANSION Renesas Technology expands the 3850 group (spec.A QzROM version) as follows. Memory Size * ROM size ................................................................ 16 K bytes * RAM size ...................................................................512 bytes Packages * PRDP0042BA-A .......................... 42-pin plastic-molded SDIP * 42P2R-A/E ...................................42-pin plastic-molded SSOP Memory Type Support for QzROM version. Memory Expansion Plan ROM size (bytes) ROM external 32K 28K 24K 20K 16K M38503G4A 12K 8K 384 512 640 768 896 1024 1152 1280 1408 1536 2048 RAM size (bytes) Fig 4. Memory expansion plan Table 2 Support products (spec.A QzROM version) Product name M38503G4A-XXXSP M38503G4A-XXXFP M38503G4ASP M38503G4AFP NOTES: ROM size (bytes) RAM size Package ROM size for User in ( ) (bytes) 16384 PRDP0042BA-A 512 (16253) 42P2R-A/E 16384 PRDP0042BA-A 512 (16253) 42P2R-A/E 1. This means a shipment of which User ROM has been programmed. The user ROM area of a blank product is blank. Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 5 of 59 Remarks QzROM version (Programmed shipment) (1) QzROM version (blank) (1) 3850 Group (Spec.A QzROM version) GROUP DESCRIPTION The QzROM version, mask ROM version and the flash memory version of 3850 group (Spec.A) are mass production. Currently support products are listed below. Table 3 Support products (mask ROM version and flash memory version of Spec.A) Product name M38503M2A-XXXSP M38503M2A-XXXFP M38503M4A-XXXSP M38503M4A-XXXFP M38504M6A-XXXSP M38504M6A-XXXFP M38507M8A-XXXSP M38507M8A-XXXFP M38507F8ASP M38507F8AFP Table 4 ROM size (bytes) RAM size Package ROM size for User in ( ) (bytes) 8192 PRDP0042BA-A 512 (8062) 42P2R-A/E 16384 PRDP0042BA-A 512 (16254) 42P2R-A/E 24576 PRDP0042BA-A 640 (24446) 42P2R-A/E 32768 PRDP0042BA-A 1024 (32635) 42P2R-A/E PRDP0042BA-A 32768 1024 42P2R-A/E Remarks Mask ROM version Flash memory version Differences among 3850 group (standard), 3850 group (spec.H), and 3850 group (spec.A) 3850 group (standard)(1) Serial interface 1: Serial I/O (UART1 or Clocksynchronized) A/D converter Unserviceable in lowspeed mode Analog input: 5 channels LED port 5: P13-P17 Software pull-up resistor Not available Absolute Power source -0.3 to 7.0 V maximum voltage ratings CNVSS -0.3 to 13.0 V input voltage Maximum operating 8.0 MHz frequency(2) Minimum operating 2.7 V power source voltage(2) NOTES: 3850 group (spec.H)(1) 2: Serial I/O1 (UART1 or Clock-synchronized) Serial I/O2 (Clocksynchronized) Serviceable in low-speed mode Analog input: 5 channels 8: P10-P17 Not available -0.3 to 6.5 V -0.3 to VCC + 0.3 V 3850 group (spec.A) Mask ROM version QzROM version Flash memory version 2: Serial I/O1 (UART1 or Clocksynchronized) Serial I/O2 (Clock-synchronized) Serviceable in low-speed mode Analog input: 9 channels 8: P10-P17 Built-in (Port P0-P4) -0.3 to 6.5 V -0.3 to 8.0 V 8.0 MHz -0.3 to VCC + 0.3 V 12.5 MHz 2.7 V 2.7 V 1.8 V 1. We are currently not receiving an new order for the standard version and Spec.H. We are currently receiving an new order for Spec.A. 2. For detail of the absolute maximum ratings, the electrical characteristics, and the recommended operating conditions, refer to each datasheet. Notes on differences among 3850 group (standard), 3850 group (spec.H), and 3850 group (spec.A) (1) The absolute maximum ratings of 3850 group (spec.A) is smaller than that of 3850 group (standard). * Power source voltage VCC = -0.3 to 6.5 V * CNVSS input voltage VI = -0.3 to VCC +0.3 V (QzROM : 8.0V) (2) The oscillation circuit constants of XIN-XOUT, XCIN-XCOUT may be some differences among 3850 group (standard), 3850 group (spec.H), and 3850 group (spec.A). Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 6 of 59 (3) Do not write any data to the reserved area and the reserved bit. (Do not change the contents after reset.) (4) Fix bit 3 of the CPU mode register to "1". (5) Be sure to perform the termination of unused pins. 3850 Group (Spec.A QzROM version) FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) The 3850 group (spec.A) uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instructions can be used. [Accumulator (A)] The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator. [Index Register X (X)] The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address. [Index Register Y (Y)] The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address. b7 [Stack Pointer (S)] The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is "0", the high-order 8 bits becomes "0016". If the stack page selection bit is "1", the high-order 8 bits becomes "0116". The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure.6. Store registers other than those described in Figure.6 with program when the user needs them during interrupts or subroutine calls. [Program Counter (PC)] The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed. b0 A b7 Accumulator b0 X b7 Index register X b0 Y b7 Index register Y b0 S b7 b15 b0 PCL PCH Stack pointer Program counter b7 b0 N V T B D I Z C Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag Fig 5. 740 Family CPU register structure Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 7 of 59 3850 Group (Spec.A QzROM version) On-going Routine Interrupt request (Note) M(S)(PCH) Push return address on stack (S)(S) - 1 Execute JSR M(S)(PCL) Push return address on stack M(S)(PCH) (S)(S) - 1 Push contents of processor status register on stack (S)(S) - 1 M(S)(PS) M(S)(PCL) (S)(S) - 1 (S)(S) - 1 Interrupt Service Routine ..... Subroutine I Flag is set from "0" to "1" Fetch the jump vector ..... Execute RTI Execute RTS (S)(S) + 1 POP return address from stack (S)(S) + 1 POP contents of processor status register from stack (PS)M(S) (PCL)M(S) (S)(S) + 1 (S)(S) + 1 (PCL)M(S) (PCH)M(S) POP return address from stack (S)(S) + 1 (PCH)M(S) Note : Condition for acceptance of an interrupt Interrupt enable flag is "1" Interrupt disable flag is "0" Fig 6. Table 5 Register push and pop at interrupt generation and subroutine call Push and pop instructions of accumulator or processor status register Push instruction to stack PHA PHP Accumulator Processor status register Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 8 of 59 Pop instruction from stack PLA PLP 3850 Group (Spec.A QzROM version) [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always "0". When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to "1". Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. Bit 5: Index X mode flag (T) When the T flag is "0", arithmetic operations are performed between accumulator and memory. When the T flag is "1", direct arithmetic operations and direct data transfers are enabled between memory locations. Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is "0", and cleared if the result is anything other than "0". Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to - 128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is "1". Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is "0"; decimal arithmetic is executed when it is "1". Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic. Table 6 Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Set and clear instructions of each bit of processor status register Set instruction Clear instruction C flag SEC CLC Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Z flag - - Page 9 of 59 I flag SEI CLI D flag SED CLD B flag - - T flag SET CLT V flag - CLV N flag - - 3850 Group (Spec.A QzROM version) [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit, the internal system clock control bits, etc. The CPU mode register is allocated at address 003B16. b7 b0 1 CPU mode register (CPUM: address 003B16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : 1 0 : Not available 1 1 : Stack page selection bit 0 : 0 page 1 : 1 page Fix this bit to "1". Port XC switch bit 0 : I/O port function (stop oscillating) 1 : XCIN-XCOUT oscillating function Main clock (XIN-XOUT) stop bit 0 : Oscillating 0 : Stopped Main clock division ratio selection bits b7 b6 0 0 : = f(XIN)/2 (high-speed mode) 0 1 : = f(XIN)/8 (middle-speed mode) 1 0 : = f(XCIN)/2 (low-speed mode) 1 1 : Not available Fig 7. Structure of CPU mode register Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 10 of 59 3850 Group (Spec.A QzROM version) MEMORY * Special Function Register (SFR) Area The Special Function Register area in the zero page contains control registers such as I/O ports and timers. * RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. * ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. In the QzROM version, 1 byte of address FFDB 16 is also a reserved area. * Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. * Zero Page Access to this area with only 2 bytes is possible in the zero page addressing mode. * ROM Code Protect Address (address FFDB16) Address FFDB16, which is the reserved ROM area of QzROM, is the ROM code protect address. "0016" is written into this address when selecting the protect bit write by using a serial programmer or selecting protect enabled for writing shipment by Renesas Technology corp.. When "0016" is set to the ROM code protect address, the protect function is enabled, so that reading or writing from/to QzROM is disabled by a serial programmer. As for the QzROM product in blank, the ROM code is protected by selecting the protect bit write at ROM writing with a serial programmer. As for the QzROM product shipped after writing, "0016" (protect enabled) or "FF16" (protect disabled) is written into the ROM code protect address when Renesas Technology corp. performs writing. The writing of "0016" or "FF16" can be selected as ROM option setup ("MASK option" written in the mask file converter) when ordering. <Notes> Since the contents of RAM are undefined at reset, be sure to set an initial value before use. * Special Page Access to this area with only 2 bytes is possible in the special page addressing mode. RAM area RAM size (bytes) Address XXXX16 000016 192 256 384 512 640 768 896 1024 1536 2048 00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16 063F16 083F16 004016 User ROM area SFR area RAM Zero page 010016 XXXX16 Not used 0FF016 0FFF16 Reserved ROM area (Note 1) Not used Fig 8. ROM area ROM size (bytes) Address YYYY16 Address ZZZZ16 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016 F08016 E08016 D08016 C08016 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016 Memory map diagram Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 11 of 59 YYYY16 Reserved ROM area (128 bytes) ZZZZ16 ROM FF0016 FFDB16 Reserved ROM area (Note 2) (ROM code protect address) FFDC16 Interrupt vector area FFFE16 FFFF16 Reserved ROM area Note 1: Flash memory version only 2: QzROM version only Special page 3850 Group (Spec.A QzROM version) 000016 Port P0 (P0) 002016 Prescaler 12 (PRE12) 000116 Port P0 direction register (P0D) 002116 Timer 1 (T1) 000216 Port P1 (P1) 002216 Timer 2 (T2) 000316 Port P1 direction register (P1D) 002316 Timer XY mode register (TM) 000416 Port P2 (P2) 002416 Prescaler X (PREX) 000516 Port P2 direction register (P2D) 002516 Timer X (TX) 000616 Port P3 (P3) 002616 Prescaler Y (PREY) 000716 Port P3 direction register (P3D) 002716 Timer Y (TY) 000816 Port P4 (P4) 002816 Timer count source selection register (TCSS) 000916 Port P4 direction register (P4D) 002916 000A16 002A16 000B16 002B16 Reserved * 000C16 002C16 Reserved * 000D16 002D16 Reserved * 000E16 002E16 Reserved * 000F16 002F16 Reserved * 001016 003016 Reserved * 001116 003116 Reserved * 001216 Port P0, P1, P2 pull-up control register (PULL012) 003216 001316 Port P3 pull-up control register (PULL3) 003316 001416 Port P4 pull-up control register (PULL4) 003416 AD control register (ADCON) 001516 Serial I/O2 control register 1 (SIO2CON1) 003516 AD conversion low-order register (ADL) 001616 Serial I/O2 control register 2 (SIO2CON2) 003616 AD conversion high-order register (ADH) 001716 Serial I/O2 register (SIO2) 003716 AD input selection register (ADSEL) 001816 Transmit/Receive buffer register (TB/RB) 003816 MISRG 001916 Serial I/O1 status register (SIOSTS) 003916 Watchdog timer control register (WDTCON) 001A16 Serial I/O1 control register (SIOCON) 003A16 Interrupt edge selection register (INTEDGE) 001B16 UART control register (UARTCON) 003B16 CPU mode register (CPUM) 001C16 Baud rate generator (BRG) 003C16 Interrupt request register 1 (IREQ1) 001D16 PWM control register (PWMCON) 003D16 Interrupt request register 2 (IREQ2) 001E16 PWM prescaler (PREPWM) 003E16 Interrupt control register 1 (ICON1) 001F16 PWM register (PWM) 003F16 Interrupt control register 2 (ICON2) 0FFE16 Reserved * * Reserved : Do not write any data to this addresses, because these areas are reserved. Fig 9. Memory map of special function register (SFR) Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 12 of 59 3850 Group (Spec.A QzROM version) I/O PORTS The I/O ports have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. When "0" is written to the bit corresponding to a pin, that pin becomes an input pin. When "1" is written to that bit, that pin becomes an output pin. If data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. Table 7 By setting the port P0, P1, P2 pull-up control register (address 001216), the port P3 pull-up control register (address 001316), or the port P4 pull-up control register (address 001416), ports can control pull-up with a program. However, the contents of these registers do not affect ports programmed as the output ports. I/O port function Pin P00/SIN2 P01/SOUT2 P02/SCLK2 P03/SRDY2 Name Port P0 Input/Out put I/O Structure Input/out CMOS compatible input Serial I/O2 function I/O put, level individual CMOS 3-state output bits P04/AN5- P07/AN8 P10-P17 Port P1 P20/XCOUT P21/XCIN Port P2 Non-Port Function Related SFRs Ref.No. Serial I/O2 control register (1) (2) (3) (4) A/D converter input AD control register AD input selection register (13) Sub-clock generating circuit CPU mode register (6) (7) (5) P22 P23 CMOS compatible input level N-channel open-drain output P24/RXD P25/TXD P26/SCLK1 CMOS compatible input Serial I/O1 function I/O level CMOS 3-state output Serial I/O1 control register (9) (10) (11) Serial I/O1 function I/O Timer X function I/O Serial I/O1 control register Timer XY mode register (12) P27/CNTR0/ SRDY1 (8) P30/AN0- P34/AN4 Port P3(1) A/D converter input AD control register AD input selection register (13) P40/CNTR1 Port P4(1) Timer Y function I/O Timer XY mode register (14) P41/INT0 P42/INT1 External interrupt input Interrupt edge selection register (15) P43/INT2/ SCMP2 External interrupt input SCMP2 output Interrupt edge selection register Serial I/O2 control register (16) P44/INT3/ PWM External interrupt input PWM output Interrupt edge selection register PWM control register (17) NOTES: 1. When bits 5 to 7 of Ports P3 and P4 are read out, the contents are undefined. Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 13 of 59 3850 Group (Spec.A QzROM version) (1) Port P00 (2) Port P01 Pull-up control bit Direction register Data bus Pull-up control bit P01/SOUT2 P-channel output disable bit Serial I/O2 Transmit completion signal Serial I/O2 port selection bit Direction register Port latch Port latch Data bus Serial I/O2 input Serial I/O2 output (4) Port P03 (3) Port P02 Pull-up control bit Pull-up control bit P02/SCLK2 P-channel output disable bit SRDY2 output enable bit Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit Direction register Direction register Data bus Data bus Port latch Port latch Serial I/O2 ready output Serial I/O2 clock output Serial I/O2 external clock input (6) Port P20 Pull-up control bit (5) Port P1 Pull-up control bit Port XC switch bit Direction register Direction register Data bus Data bus Port latch Port latch Oscillator Port P21 Port XC switch bit (7) Port P21 Pull-up control bit Port XC switch bit Direction register Data bus (8) Ports P22, P23 Direction register Port latch Data bus Sub-clock generating circuit input Fig 10. Port block diagram (1) Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 14 of 59 Port latch 3850 Group (Spec.A QzROM version) (9) Port P24 (10) Port P25 Pull-up control bit Pull-up control bit Serial I/O1 enable bit Receive enable bit P-channel output disable bit Serial I/O1 enable bit Transmit enable bit Direction register Data bus Direction register Port latch Data bus Port latch Serial I/O1 input Serial I/O1 output (12) Port P27 (11) Port P26 Pull-up control bit Serial I/O1 synchronous clock selection bit Serial I/O1 enable bit Serial I/O1 mode selection bit Serial I/O1 enable bit Direction register Direction register Data bus Data bus Pull-up control bit Pulse output mode Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit Port latch Port latch Pulse output mode Serial ready output Serial I/O1 clock output (13) Ports P04-P07, P30-P34 (14) Port P40 Pull-up control bit Pull-up control bit Direction register Direction register Data bus Data bus CNTR0 interrupt input Timer output Serial I/O1 external clock input Port latch Port latch Pulse output mode Timer output A/D converter input Analog input pin selection bit Analog input port selection switch bit (15) Ports P41, P42 CNTR1 interrupt input (16) Port P43 Pull-up control bit Pull-up control bit Serial I/O2 I/O comparison signal control bit Direction register Data bus Direction register Port latch Data bus Interrupt input Port latch Serial I/O2 I/O comparison signal output Interrupt input Fig 11. Port block diagram (2) Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 15 of 59 3850 Group (Spec.A QzROM version) (17) Port P44 Pull-up control bit PWM function enable bit Direction register Data bus Port latch PWM output Interrupt input Fig 12. Port block diagram (3) Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 16 of 59 3850 Group (Spec.A QzROM version) b7 b0 Port P0, P1, P2 pull-up control register (PULL012: address 0012 16) P0 pull-up control bit 0: No pull-up 1: Pull-up P1 pull-up control bit Note: Pull-up control is valid when the corresponding bit 0: No pull-up of the port direction register is "0" (input). 1: Pull-up When that bit is "1" (output), pull-up cannot be set P2 pull-up control bit to the port of which pull-up is selected. 0: No pull-up 1: Pull-up Not used (return "0" when read) b7 b0 Port P3 pull-up control register (PULL3: address 001316) P30 pull-up control bit 0: No pull-up 1: Pull-up P31 pull-up control bit 0: No pull-up 1: Pull-up P32 pull-up control bit 0: No pull-up 1: Pull-up P33 pull-up control bit 0: No pull-up 1: Pull-up P34 pull-up control bit 0: No pull-up 1: Pull-up Fix these bits to "0". Fig 13. Structure of port registers (1) Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 17 of 59 Note: Pull-up control is valid when the corresponding bit of the port direction register is "0" (input). When that bit is "1" (output), pull-up cannot be set to the port of which pull-up is selected. 3850 Group (Spec.A QzROM version) b7 b0 Port P4 pull-up control register (PULL4 : address 001416) P40 pull-up control bit 0: No pull-up 1: Pull-up P41 pull-up control bit 0: No pull-up 1: Pull-up P42 pull-up control bit 0: No pull-up 1: Pull-up P43 pull-up control bit 0: No pull-up 1: Pull-up P44 pull-up control bit 0: No pull-up 1: Pull-up Fix these bits to "0". Fig 14. Structure of port registers (2) Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 18 of 59 Note: Pull-up control is valid when the corresponding bit of the port direction register is "0" (input). When that bit is "1" (output), pull-up cannot be set to the port of which pull-up is selected. 3850 Group (Spec.A QzROM version) INTERRUPTS Interrupts occur by 15 sources among 15 sources: six external, eight internal, and one software. * Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are "1" and the interrupt disable flag is "0". Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction cannot be disabled with any flag or bit. The I (interrupt disable) flag disables all interrupts except the BRK instruction interrupt. When several interrupts occur at the same time, the interrupts are received according to priority. * Interrupt Operation By acceptance of an interrupt, the following operations are automatically performed: 1. The contents of the program counter and the processor status register are automatically pushed onto the stack. 2. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. The interrupt jump destination address is read from the vector table into the program counter. Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 19 of 59 <Notes> When setting the followings, the interrupt request bit may be set to "1". * When setting external interrupt active edge Related register: Interrupt edge selection register (address 003A16) Timer XY mode register (address 002316) * When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated Related register: Interrupt edge selection register (address 003A16) When not requiring for the interrupt occurrence synchronized with these setting, take the following sequence. (1) Set the corresponding interrupt enable bit to "0" (disabled). (2) Set the interrupt edge select bit (the active edge selection bit) or the interrupt source select. (3) Set the corresponding interrupt request bit to "0" after 1 or more instructions have been executed. (4) Set the corresponding interrupt enable bit to "1" (enabled). 3850 Group (Spec.A QzROM version) Table 8 Interrupt vector addresses and priority Reset(2) INT0 1 Vector Interrupt Request Generating Addresses(1) Conditions High Low FFFD16 FFFC16 At reset 2 FFFB16 FFFA16 Reserved INT1 3 4 FFF916 FFF716 FFF816 FFF616 INT2 5 FFF516 FFF416 INT3/Serial I/O2 6 FFF316 FFF216 Reserved Timer X Timer Y Timer 1 Timer 2 Serial I/O1 reception 7 8 9 10 11 12 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 Serial I/O1 Transmission 13 FFE516 FFE416 CNTR0 14 FFE316 FFE216 CNTR1 15 FFE116 FFE016 Interrupt Source Priority At detection of either rising or falling edge of INT0 input Reserved At detection of either rising or falling edge of INT1 input At detection of either rising or falling edge of INT2 input At detection of either rising or falling edge of INT3 input/ At completion of serial I/O2 data reception/transmission Reserved At timer X underflow At timer Y underflow At timer 1 underflow At timer 2 underflow At completion of serial I/O1 data reception At completion of serial I/O1 transfer shift or when transmission buffer is empty At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of CNTR1 input At completion of A/D conversion At BRK instruction execution A/D converter 16 FFDF16 FFDE16 BRK instruction 17 FFDD16 FFDC16 NOTES: 1. Vector addresses contain interrupt jump destination addresses. 2. Reset function in the same way as an interrupt with the highest priority. Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 20 of 59 Remarks Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Switch by Serial I/O2/INT3 interrupt source bit STP release timer underflow Valid when serial I/O1 is selected Valid when serial I/O1 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) Non-maskable software interrupt 3850 Group (Spec.A QzROM version) Interrupt request bit Interrupt enable bit Interrupt disable flag (I) BRK instruction Reset Interrupt request Fig 15. Interrupt control b7 b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 interrupt edge selection bit INT1 interrupt edge selection bit 0 : Falling edge active INT2 interrupt edge selection bit 1 : Rising edge active INT3 interrupt edge selection bit Serial I/O2 / INT3 interrupt source bit 0 : INT3 interrupt selected 1 : Serial I/O2 interrupt selected Not used (returns "0" when read) b7 b7 b0 b0 Interrupt request register 1 (IREQ1 : address 003C16) b7 b0 Interrupt request register 2 (IREQ2 : address 003D16) INT0 interrupt request bit Reserved INT1 interrupt request bit INT2 interrupt request bit INT3 / Serial I/O2 interrupt request bit Reserved Timer X interrupt request bit Timer Y interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit Serial I/O1 reception interrupt request bit Serial I/O1 transmit interrupt request bit CNTR0 interrupt request bit CNTR1 interrupt request bit AD converter interrupt request bit Not used (returns "0" when read) 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued Interrupt control register 1 (ICON1 : address 003E16) b7 b0 Interrupt control register 2 (ICON2 : address 003F16) INT0 interrupt enable bit Reserved (Do not write "1" to this bit.) INT1 interrupt enable bit INT2 interrupt enable bit INT3 / Serial I/O2 interrupt enable bit Reserved (Do not write "1" to this bit.) Timer X interrupt enable bit Timer Y interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit Serial I/O1 reception interrupt enable bit Serial I/O1 transmit interrupt enable bit CNTR0 interrupt enable bit CNTR1 interrupt enable bit AD converter interrupt enable bit Not used (returns "0" when read) (Do not write "1" to this bit.) 0 : Interrupts disabled 1 : Interrupts enabled 0 : Interrupts disabled 1 : Interrupts enabled Fig 16. Structure of interrupt-related registers Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 21 of 59 3850 Group (Spec.A QzROM version) TIMERS The 3850 group (spec.A) has four timers: timer X, timer Y, timer 1, and timer 2. The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. All timers are count down. When the timer reaches "0016", an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to "1". b7 b0 Timer XY mode register (TM : address 002316) Timer X operating mode bit b1 b0 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR0 active edge selection bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer X count stop bit 0: Count start 1: Count stop Timer Y operating mode bits b5 b4 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR1 active edge selection bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer Y count stop bit 0: Count start 1: Count stop Fig 17. Structure of timer XY mode register b7 b0 Timer count source selection register (TCSS : address 002816) Timer X count source selection bit 0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode) 1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode) Timer Y count source selection bit 0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode) 1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode) Timer 12 count source selection bit 0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode) 1 : f(XCIN) Not used (returns "0" when read) Fig 18. Structure of timer count source selection register Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 22 of 59 * Timer 1 and Timer 2 The count source of prescaler 12 is the oscillation frequency which is selected by timer 12 count source selection bit. The output of prescaler 12 is counted by timer 1 and timer 2, and a timer underflow sets the interrupt request bit. * Timer X and Timer Y Timer X and Timer Y can each select in one of four operating modes by setting the timer XY mode register. (1) Timer Mode The timer counts the count source selected by Timer count source selection bit. (2) Pulse Output Mode The timer counts the count source selected by Timer count source selection bit. Whenever the contents of the timer reach "0016", the signal output from the CNTR0 (or CNTR1 ) pin is inverted. If the CNTR0 (or CNTR1) active edge selection bit is "0", output begins at "H". If it is "1", output starts at "L". When using a timer in this mode, set the corresponding port P27 (or port P40) direction register to output mode. (3) Event Counter Mode Operation in event counter mode is the same as in timer mode, except that the timer counts signals input through the CNTR0 or CNTR1 pin. When the CNTR0 (or CNTR1) active edge selection bit is "0", the rising edge of the CNTR0 (or CNTR1) pin is counted. When the CNTR0 (or CNTR1) active edge selection bit is "1", the falling edge of the CNTR0 (or CNTR1) pin is counted. (4) Pulse Width Measurement Mode If the CNTR0 (or CNTR1) active edge selection bit is "0", the timer counts the selected signals by the count source selection bit while the CNTR0 (or CNTR1) pin is at "H". If the CNTR0 (or CNTR1) active edge selection bit is "1", the timer counts it while the CNTR0 (or CNTR1) pin is at "L". The count can be stopped by setting "1" to the timer X (or timer Y) count stop bit in any mode. The corresponding interrupt request bit is set each time a timer underflows. <Notes> When switching the count source by the timer 12, X and Y count source bits, the value of timer count is altered in unconsiderable amount owing to generating of a thin pulses in the count input signals. Therefore, select the timer count source before set the value to the prescaler and the timer. When timer X/timer Y underflow while executing the instruction which sets "1" to the timer X/timer Y count stop bits, the timer X/ timer Y interrupt request bits are set to "1". Timer X/Timer Y interrupts are received if these interrupts are enabled at this time. The timing which interrupt is accepted has a case after the instruction which sets "1" to the count stop bit, and a case after the next instruction according to the timing of the timer underflow. When this interrupt is unnecessary, set "0" (disabled) to the interrupt enable bit and then set "1" to the count stop bit. 3850 Group (Spec.A QzROM version) Data bus f(XIN)/16 (f(XCIN)/16 at low-speed mode) Prescaler X latch (8) f(XIN)/2 Pulse width Timer mode (f(XCIN)/2 at low-speed mode) measurement Pulse output mode Timer X count source mode selection bit Prescaler X (8) CNTR0 active edge Event selection bit Timer X count stop bit counter P27/CNTR0 "0" mode Timer X latch (8) Timer X (8) To timer X interrupt request bit To CNTR0 interrupt request bit "1" CNTR0 active edge "1" selection bit "0" Port P27 latch Port P27 direction register Q Toggle flip-flop T Q R Timer X latch write pulse Pulse output mode Pulse output mode Data bus f(XIN)/16 (f(XCIN)/16 at low-speed mode) f(XIN)/2 (f(XCIN)/2 at low-speed mode) Prescaler Y latch (8) Pulse width Timer mode measurement Pulse output mode Timer Y count source mode selection bit Prescaler Y (8) CNTR1 active edge selection bit "0" P40/CNTR1 Event counter mode Timer Y latch (8) Timer Y (8) To timer Y interrupt request bit Timer Y count stop bit To CNTR1 interrupt request bit "1" CNTR1 active edge "1" selection bit Q Toggle flip-flop T Q "0" Port P40 latch Port P40 direction register R Timer Y latch write pulse Pulse output mode Pulse output mode Data bus Prescaler 12 latch (8) f(XIN)/16 (f(XCIN)/16 at low-speed mode) Prescaler 12 (8) f(XCIN) Timer 12 count source selection bit Fig 19. Block diagram of timer X, timer Y, timer 1, and timer 2 Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 23 of 59 Timer 1 latch (8) Timer 2 latch (8) Timer 1 (8) Timer 2 (8) To timer 2 interrupt request bit To timer 1 interrupt request bit 3850 Group (Spec.A QzROM version) SERIAL INTERFACE * Serial I/O1 Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O1. A dedicated timer is also provided for baud rate generation. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O mode can be selected by setting the serial I/O1 mode selection bit of the serial I/O1 control register (bit 6 of address 001A16) to "1". For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB. Data bus Serial I/O1 control register Address 001816 Receive buffer register Receive buffer full flag (RBF) Receive shift register P24/RXD Address 001A16 Receive interrupt request (RI) Shift clock Clock control circuit P26/SCLK1 XIN Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) BRG count source selection bit Baud rate generator 1/4 Address 001C16 1/4 P27/SRDY1 F/F Falling-edge detector Clock control circuit Shift clock P25/TXD Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit shift register Transmit buffer register Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001816 Address 001916 Data bus Fig 20. Block diagram of clock synchronous serial I/O1 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TXD D0 D1 D2 D3 D4 D5 D6 D7 Serial input RXD D0 D1 D2 D3 D4 D5 D6 D7 Receive enable signal SRDY1 Write pulse to receive/transmit buffer register (address 001816) TBE = 0 TBE = 1 TSC = 0 RBF = 1 TSC = 1 Overrun error (OE) detection Notes 1: As the transmit interrupt (TI), either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TXD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1". Fig 21. Operation of clock synchronous serial I/O1 function Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 24 of 59 3850 Group (Spec.A QzROM version) (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit (b6) of the serial I/O1 control register to "0". Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Data bus Address 001816 Receive buffer register OE Serial I/O1 control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) Character length selection bit P24/RXD ST detector 7 bits Receive shift register 1/16 8 bits PE FE UART control register SP detector Address 001B16 Clock control circuit Serial I/O1 synchronous clock selection bit P26/SCLK1 BRG count source selection bit Frequency division ratio 1/(n+1) XIN Baud rate generator Address 001C16 1/4 ST/SP/PA generator 1/16 P25/TXD Transmit shift register Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Character length selection bit Transmit buffer register Address 001816 Data bus Fig 22. Block diagram of UART serial I/O1 Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 25 of 59 Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 3850 Group (Spec.A QzROM version) Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output TXD TBE=0 TBE=1 ST D0 D1 SP TSC=1* ST D0 D1 SP Generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) Receive buffer read signal RBF=0 RBF=1 Serial input RXD ST D0 D1 SP RBF=1 ST D0 D1 SP Notes 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes "1", can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes "1". 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. Fig 23. Operation of UART serial I/O1 function [Transmit Buffer Register/Receive Buffer Register (TB/RB)] 001816 The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is "0". [Serial I/O1 Status Register (SIOSTS)] 001916 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O1 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to "0" when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing "0" to the serial I/O1 enable bit SIOE (bit 7 of the serial I/O1 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O1 status register are initialized to "0" at reset, but if the transmit enable bit (bit 4) of the serial I/O1 control register has been set to "1", the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become "1". Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 26 of 59 [Serial I/O1 Control Register (SIOCON)] 001A16 The serial I/O1 control register consists of eight control bits for the serial I/O1 function. [UART Control Register (UARTCON)] 001B16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer and one bit (bit 4) which is al-ways valid and sets the output structure of the P25/TXD pin. [Baud Rate Generator (BRG)] 001C16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. 3850 Group (Spec.A QzROM version) b7 b0 Serial I/O1 status register (SIOSTS : address 001916) b7 Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns "1" when read) b7 b0 UART control register (UARTCON : address 001B16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P25/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return "1" when read) Fig 24. Structure of serial I/O1 control registers <Notes on serial interface> When setting the transmit enable bit to "1", the serial I/O1 transmit interrupt request bit is automatically set to "1". When not requiring the interrupt occurrence synchronized with the transmission enabled, take the following sequence. (1) Set the serial I/O1 transmit interrupt enable bit to "0" (disabled). (2) Set the transmit enable bit to "1". (3) Set the serial I/O1 transmit interrupt request bit to "0" after 1 or more instructions have been executed. (4) Set the serial I/O1 transmit interrupt enable bit to "1" (enabled). Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 27 of 59 b0 Serial I/O1 control register (SIOCON : address 001A16) BRG count source selection bit (CSS) 0: f(XIN) 1: f(XIN)/4 Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O1 is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O1 is selected, external clock input divided by 16 when UART is selected. SRDY1 output enable bit (SRDY) 0: P27 pin operates as ordinary I/O pin 1: P27 pin operates as SRDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P24 to P27 operate as ordinary I/O pins) 1: Serial I/O1 enabled (pins P24 to P27 operate as serial I/O1 pins) 3850 Group (Spec.A QzROM version) * Serial I/O2 The serial I/O2 can be operated only as the clock synchronous type. As a synchronous clock for serial transfer, either internal clock or external clock can be selected by the serial I/O2 synchronous clock selection bit (b6) of serial I/O2 control register 1. The internal clock incorporates a dedicated divider and permits selecting 6 types of clock by the internal synchronous clock selection bits (b2, b1, b0) of serial I/O2 control register 1. Regarding SOUT2 and SCLK2 being output pins, either CMOS output format or N-channel open-drain output format can be selected by the P01/SOUT2, P02/SCLK2 P-channel output disable bit (b7) of serial I/O2 control register 1. When the internal clock has been selected, a transfer starts by a write signal to the serial I/O2 register (address 001716). After completion of data transfer, the level of the SOUT2 pin goes to high impedance automatically but bit 7 of the serial I/O2 control register 2 is not set to "1" automatically. When the external clock has been selected, the contents of the serial I/O2 register is continuously shifted while transfer clocks are input. Accordingly, control the clock externally. Note that the SOUT2 pin does not go to high impedance after completion of data transfer. To cause the S OUT2 pin to go to high impedance in the case where the external clock is selected, set bit 7 of the serial I/O2 control register 2 to "1" when SCLK2 is "H" after completion of data transfer. After the next data transfer is started (the transfer clock falls), bit 7 of the serial I/O2 control register 2 is set to "0" and the SOUT2 pin is put into the active state. Regardless of the internal clock to external clock, the interrupt request bit is set after the number of bits (1 to 8 bits) selected by the optional transfer bit is transferred. In case of a fractional number of bits less than 8 bits as the last data, the received data to be stored in the serial I/O2 register becomes a fractional number of bits close to MSB if the transfer direction selection bit of serial I/O2 control register 1 is LSB first, or a fractional number of bits close to LSB if the transfer direction selection bit is MSB first. For the remaining bits, the previously received data is shifted. At transmit operation using the clock synchronous serial I/O, the SCMP2 signal can be output by comparing the state of the transmit pin SOUT2 with the state of the receive pin SIN2 in synchronization with a rise of the transfer clock. If the output level of the SOUT2 pin is equal to the input level to the SIN2 pin, "L" is output from the SCMP2 pin. If not, "H" is output. At this time, an INT2 interrupt request can also be generated. Select a valid edge by bit 2 of the interrupt edge selection register (address 003A16). [Serial I/O2 Control Registers 1, 2 (SIO2CON1 / SIO2CON2)] 001516, 001616 The serial I/O2 control registers 1 and 2 are containing various selection bits for serial I/O2 control as shown in Figure.25. Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 28 of 59 b7 b0 Serial I/O2 control register 1 (SIO2CON1 : address 001516) Internal synchronous clock selection bits b2 b1 b0 0 0 0: f(XIN)/8 (f(XCIN)/8 in low-speed mode) 0 0 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode) 0 1 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode) 0 1 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode) 1 1 0: f(XIN)/128 f(XCIN)/128 in low-speed mode) 1 1 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode) Serial I/O2 port selection bit 0: I/O port 1: SOUT2, SCLK2 output pin SRDY2 output enable bit 0: P03 pin is normal I/O pin 1: P03 pin is SRDY2 output pin Transfer direction selection bit 0: LSB first 1: MSB first Serial I/O2 synchronous clock selection bit 0: External clock 1: Internal clock P01/SOUT2, P02/SCLK2 P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) b7 b0 Serial I/O2 control register 2 (SIO2CON2 : address 001616) Optional transfer bits b2 b1 b0 0 0 0: 1 bit 0 0 1: 2 bit 0 1 0: 3 bit 0 1 1: 4 bit 1 0 0: 5 bit 1 0 1: 6 bit 1 1 0: 7 bit 1 1 1: 8 bit Not used (returns "0" when read) Serial I/O2 I/O comparison signal control bit 0: P43 I/O 1: SCMP2 output SOUT2 pin control bit (P01) 0: Output active 1: Output high-impedance Fig 25. Structure of Serial I/O2 control registers 1, 2 3850 Group (Spec.A QzROM version) XCIN 1/16 Divider "10" Main clock division ratio selection bits (Note) "00" "01" XIN P03 latch S CLK2 SRDY2 Synchronous circuit "1" SRDY2 output enable bit Serial I/O2 synchronous clock selection bit Data bus 1/32 1/64 1/128 1/256 Serial I/O2 synchronous clock selection bit "1" "0" P03/SRDY2 Internal synchronous clock selection bits 1/8 "0" External clock P02 latch Optional transfer bits (3) "0" P02/SCLK2 Serial I/O2 interrupt request Serial I/O counter 2 (3) "1" Serial I/O2 port selection bit P01 latch "0" P01/SOUT2 "1" Serial I/O2 port selection bit Serial I/O2 register (8) P00/SIN2 P43 latch "0" P43/SCMP2/INT2 "1" Serial I/O2 I/O comparison signal control bit D Q Note: Either high-speed, middle-speed or low-speed mode is selected by bits 6 and 7 of CPU mode register. Fig 26. Block diagram of Serial I/O2 Transfer clock (Note 1) Write-in signal to serial I/O2 register (Note 2) Serial I/O2 output SOUT2 D0 D1 D2 D3 D4 D5 D6 D7 Serial I/O2 input SIN2 Receive enable signal SRDY2 Serial I/O2 interrupt request bit set Notes1: When the internal clock is selected as a transfer clock, the f(XIN) clock division (f(XCIN) in low-speed mode) can be selected by setting bits 0 to 2 of serial I/O2 control register 1. 2: When the internal clock is selected as a transfer clock, the SOUT2 pin has high impedance after transfer completion. Fig 27. Timing chart of Serial I/O2 Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 29 of 59 3850 Group (Spec.A QzROM version) SCMP2 SCLK2 SOUT2 SIN2 Judgment of I/O data comparison Fig 28. SCMP2 output operation Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 30 of 59 3850 Group (Spec.A QzROM version) PULSE WIDTH MODULATION (PWM) The 3850 group (spec.A) has a PWM function with an 8-bit resolution, based on a signal that is the clock input XIN or that clock input divided by 2. * Data Setting The PWM output pin also functions as port P44. Set the PWM period by the PWM prescaler, and set the "H" term of output pulse by the PWM register. If the value in the PWM prescaler is n and the value in the PWM register is m (where n = 0 to 255 and m = 0 to 255): PWM period = 255 x (n+1) / f(XIN) = 31.875 x (n+1) s (when f(XIN) = 8 MHz, count source selection bit = "0") Output pulse "H" term = PWM period x m / 255 = 0.125 x (n+1) x m s (when f(XIN) = 8 MHz, count source selection bit = "0") * PWM Operation When bit 0 (PWM enable bit) of the PWM control register is set to "1", operation starts by initializing the PWM output circuit, and pulses are output starting at an "H". If the PWM register or PWM prescaler is updated during PWM output, the pulses will change in the cycle after the one in which the change was made. 31.875 x m x (n+1) 255 s PWM output T = [31.875 x (n+1)] s m : Contents of PWM register n : Contents of PWM prescaler T : PWM period (when f(XIN) = 8 MHz, count source selection bit = "0") Fig 29. Timing of PWM period Data bus PWM prescaler pre-latch PWM register pre-latch Transfer control circuit PWM prescaler latch PWM register latch PWM prescaler PWM register Count source selection bit "0" XIN (XCIN at low-speed mode) 1/2 Port P44 "1" Port P44 latch PWM function enable bit Fig 30. Block diagram of PWM function Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 31 of 59 3850 Group (Spec.A QzROM version) b7 b0 PWM control register (PWMCON : address 001D16) PWM function enable bit 0: PWM disabled 1: PWM enabled Count source selection bit 0: f(XIN) (f(XCIN) at low-speed mode) 1: f(XIN)/2 (f(XCIN)/2 at low-speed mode) Not used (return "0" when read) Fig 31. Structure of PWM control register A B C B C T = T2 PWM output T PWM register write signal T T2 (Changes "H" term from "A" to " B".) PWM prescaler write signal (Changes PWM period from "T" to "T2".) When the contents of the PWM register or PWM prescaler have changed, the PWM output will change from the next period after the change. Fig 32. PWM output timing when PWM register or PWM prescaler is changed <Notes> The PWM starts after the PWM function enable bit is set to enable and "L" level is output from the PWM pin. The length of this "L" level output is as follows: n+1 ---------------------sec 2 x f ( X IN ) (Count source selection bit = 0, where n is the value set in the prescaler) n + 1--------------sec f ( X IN ) (Count source selection bit = 1, where n is the value set in the prescaler) Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 32 of 59 3850 Group (Spec.A QzROM version) A/D CONVERTER [AD Conversion Registers (ADL, ADH)] 003516, 003616 The AD conversion registers are read-only registers that store the result of an A/D conversion. Do not read these registers during an A/D conversion. b7 b0 AD control register (ADCON : address 003416) Analog input pin selection bits [AD Control Register (ADCON)] 003416 The AD control register controls the A/D conversion process. Bits 0 to 2 select a specific analog input pin. By setting a value to these bits, when bit 0 of the AD input selection register (address 003716) is "0", P30/AN0-P34/AN4 can be selected, and when bit 0 of the AD input selection register is "1", P04/AN5-P07/AN8 can be selected. Bit 4 indicates the completion of an A/D conversion. The value of this bit remains at "0" during an A/D conversion and changes to "1" when an A/D conversion ends. Writing "0" to this bit starts the A/D conversion. [AD Input Selection Register (ADSEL)] 003716 The analog input port selection switch bit is assigned to bit 0 of the AD input selection register. When "0" is set to the analog input port selection switch bit, P30/AN0-P34/AN4 can be selected by the analog input pin selection bits (b2, b1, b0) of the AD control register (address 003416). When "1" is set to the analog input port selection switch bit, P04/AN5-P07/AN8 can be selected by the analog input pin selection bits (b2, b1, b0) of the AD control register (address 003416). b2 b1 b0 0 0 0 0 1 0 0 1 1 0 0: 1: 0: 1: 0: Note 1 P30/AN0 P31/AN1 P32/AN2 P33/AN3 P34/AN4 Note 2 or or or or P04/AN5 P05/AN6 P06/AN7 P07/AN8 Not used (returns "0" when read) AD conversion completion bit 0: Conversion in progress 1: Conversion completed Not used (returns "0" when read) Notes 1: This is selected when bit 0 of the AD input selection register (address 003716) is "0". 2: This is selected when bit 0 of the AD input selection register (address 003716) is "1". Fig 33. Structure of AD control register b7 b0 AD input selection register (ADSEL: address 003716) * Comparison Voltage Generator The comparison voltage generator divides the voltage between AVSS and VREF into 1024 and outputs the divided voltages. Analog input port selection switch bit 0: P30/AN0 to P34/AN4 is selected as analog input pin. 1: P04/AN5 to P07/AN8 is selected as analog input pin. * Channel Selector The channel selector selects one of ports P30/AN0 to P34/AN4, P04/AN5 to P07/AN8 and inputs the voltage to the comparator. Not used (returns "0" when read) Fix this bit to "0". Not used (returns "0" when read) * Comparator and Control Circuit The comparator and control circuit compare an analog input voltage with the comparison voltage, and the result is stored in the AD conversion registers. When an A/D conversion is completed, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to "1". Note that because the comparator consists of a capacitor coupling, set f(X IN ) to 500 kHz or more during an A/D conversion. When the A/D converter is operated at low-speed mode, f(XIN) and f(XCIN) do not have the lower limit of frequency, because of the A/D converter has a built-in self-oscillation circuit. Fix this bit to "0". Fig 34. Structure of AD input selection register 8-bit reading (Read only address 0035 16) (Address 003516) b7 b0 b9 b8 b7 b6 b5 b4 b3 b2 10-bit reading (Read address 003616 before 003516) (Address 003616) b7 b0 b9 b8 (Address 003516) b7 b0 b7 b6 b5 b4 b3 b2 b1 b0 Note : The high-order 6 bits of address 003616 become "0" at reading. Fig 35. Structure of AD conversion registers Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 33 of 59 3850 Group (Spec.A QzROM version) Data bus AD control register (Address 003416) b7 b0 b7 b0 AD input selection register (Address 003716) 3 A/D interrupt request A/D control circuit Channel selector P30/AN0 P31/AN1 P32/AN2 P33/AN3 P34/AN4 P04/AN5 P05/AN6 P06/AN7 P07/AN8 Comparator AD conversion high-order register (Address 003616) AD conversion low-order register (Address 003516) 10 Resistor ladder VREF AVSS Fig 36. Block diagram of A/D converter Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 34 of 59 3850 Group (Spec.A QzROM version) WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an 8-bit watchdog timer L and an 8-bit watchdog timer H. * Initial value of watchdog timer At reset or writing to the watchdog timer control register (address 0039 16 ), each of watchdog timer H and L is set to "FF16". Any instruction which generates a write signal such as the instructions of STA, LDM, CLB and others can be used to write. The data of bits 6 and 7 are only valid when writing to the watchdog timer control register. Each of watchdog timer is set to "FF16" regardless of the written data of bits 0 to 5. * Operation of Watchdog Timer The watchdog timer stops at reset and starts to count down by writing to the watchdog timer control register. An internal reset occurs at an underflow of the watchdog timer H. The reset is released after waiting for a reset release time and the program is processed from the reset vector address. Accordingly, programming is usually performed so that writing to the watchdog timer control register may be started before an underflow. If writing to the watchdog timer control register is not performed once, the watchdog timer does not function. * Bit 6 of Watchdog Timer Control Register * When bit 6 of the watchdog timer control register is "0", the MCU enters the stop mode by execution of STP instruction. Just after releasing the stop mode, the watchdog timer restarts counting (Note). When executing the WIT instruction, the watchdog timer does not stop. * When bit 6 is "1", execution of STP instruction causes an internal reset. When this bit is set to "1" once, it cannot be rewritten to "0" by program. Bit 6 is "0" at reset. The required time after writing to the watchdog timer control register to an underflow of the watchdog timer H is shown as follows. When bit 7 of the watchdog timer control register is "0": 32 s at XCIN = 32.768 kHz frequency and 65.536 ms at XIN = 16 MHz frequency. When bit 7 of the watchdog timer control register is "1": 125 ms at XCIN = 32.768 kHz frequency and 256 s at XIN = 16 MHz frequency. Note. The watchdog timer continues to count for waiting for a stop mode release time. Do not generate an underflow of the watchdog timer H during that time. "FF16" is set when watchdog timer control register is written to. XCIN "10" Main clock division ratio selection bits (Note) Data bus Watchdog timer L (8) 1/16 XIN "0" "1" "00" "01" "FF16" is set when watchdog timer control register is written to. Watchdog timer H (8) Watchdog timer H count source selection bit STP instruction function selection bit STP instruction Reset circuit RESET Internal reset Note: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register. Fig 37. Block diagram of Watchdog timer b7 b0 Watchdog timer control register (WDTCON : address 003916) Watchdog timer H (for read-out of high-order 6 bit) STP instruction function selection bit 0: Entering stop mode by execution of STP instruction 1: Internal reset by execution of STP instruction Watchdog timer H count source selection bit 0: Watchdog timer L underflow 1: f(XIN)/16 or f(XCIN)/16 Fig 38. Structure of Watchdog timer control register Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 35 of 59 3850 Group (Spec.A QzROM version) RESET CIRCUIT To reset the microcomputer, RESET pin must be held at an "L" level for 20 cycles or more of X IN . Then the RESET pin is returned to an "H" level (the power source voltage must be between 1.8 V and 5.5 V, and the oscillation must be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD16 (high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage is less than 0.28 V for VCC of 1.8 V. Poweron Power source voltage 0V VCC RESET Reset input voltage 0V (Note) 0.16VCC Note : Reset release voltage; VCC = 1.8 V VCC RESET Power source voltage detection circuit Fig 39. Reset circuit example XIN RESET RESETOUT ? Address ? ? ? FFFC FFFC ADH,L Reset address from the vector table. ? Data ? ? ? ADL ADH SYNC XIN: 8 to 13 clock cycles Notes1: The frequency relation of f(XIN) and f() is f(XIN) = 2 x f(). 2: The question marks (?) indicate an undefined state that depends on the previous state. 3: All signals except XIN and RESET are internals. Fig 40. Reset sequence Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 36 of 59 3850 Group (Spec.A QzROM version) Address Register contents Address Register contents (1) Port P0 (P0) 000016 0016 (34) AD control register (ADCON) 003416 0 0 0 1 0 0 0 0 (2) Port P0 direction register (P0D) 000116 0016 (35) AD conversion low-order register (ADL) 003516 X X X X X X X X (3) Port P1 (P1) 000216 0016 (36) AD conversion high-order register (ADH) 003616 0 0 0 0 0 0 X X (4) Port P1 direction register (P1D) 000316 0016 (37) AD input selection register (ADSEL) 003716 0016 003816 0016 003916 0 0 1 1 1 1 1 1 (5) Port P2 (P2) 000416 0016 (38) MISRG (6) Port P2 direction register (P2D) 000516 0016 (39) Watchdog timer control register (WDTCON) (7) Port P3 (P3) 000616 0016 (40) Interrupt edge selection register (INTEDGE) 003A16 (8) Port P3 direction register (P3D) 000716 0016 (41) CPU mode register (CPUM) 003B16 0 1 0 0 1 0 0 0 (9) Port P4 (P4) 000816 0016 (42) Interrupt request register 1 (IREQ1) 003C16 0016 000916 0016 (43) Interrupt request register 2 (IREQ2) 003D16 0016 (11) Port P0, P1, P2 pull-upcontrolregister (PULL012) 001216 0016 (44) Interrupt control register 1 (ICON1) 003E16 0016 (12) Port P3 pull-up control register (PULL3) 001316 0016 (45) Interrupt control register 2 (ICON2) 003F16 0016 (13) Port P4 pull-up control register (PULL4) 001416 0016 (46) Processor status register (14) Serial I/O2 control register 1 (SIO2CON1) 001516 0016 (47) Program counter (15) Serial I/O2 control register 2 (SIO2CON2) 001616 0 0 0 0 0 1 1 1 (10) Port P4 direction register (P4D) 001716 (17) Transmit/Receive buffer register (TB/RB) 001816 X X X X X X X X (18) Serial I/O1 status register (SIOSTS) 001916 1 0 0 0 0 0 0 0 (19) Serial I/O1 control register (SIOCON) 001A16 0016 (20) UART control register (UARTCON) 001B16 1 1 1 0 0 0 0 0 (21) Baud rate generator (BRG) 001C16 X X X X X X X X (22) PWM control register (PWMCON) 001D16 (23) PWM prescaler (PREPWM) 001E16 X X X X X X X X (24) PWM register (PWM) 001F16 X X X X X X X X (25) Prescaler 12 (PRE12) 002016 FF16 (26) Timer 1 (T1) 002116 0116 (27) Timer 2 (T2) 002216 0016 (28) Timer XY mode register (TM) 002316 0016 (29) Prescaler X (PREX) 002416 FF16 (30) Timer X (TX) 002516 FF16 (31) Prescaler Y (PREY) 002616 FF16 (32) Timer Y (TY) 002716 FF16 (33) Timer count source selection register (TCSS) 002816 0016 Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 37 of 59 (PS) X X X X X 1 X X (PCH) FFFD16 contents (PCL) FFFC16 contents XX X X X XX X (16) Serial I/O2 register (SIO2) Fig 41. Internal status at reset 0016 0016 Note : X : Not fixed Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set. 3850 Group (Spec.A QzROM version) CLOCK GENERATING CIRCUIT The 3850 group (spec. A QzROM version) has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between X IN and X OUT (X CIN and X COUT ). Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between XIN and X OUT since a feed-back resistor exists on-chip.(An external feed-back resistor may be needed depending on conditions.) However, an external feedback resistor is needed between XCIN and XCOUT. Immediately after power on, only the XIN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O ports. * Frequency Control (1) Middle-speed mode The internal clock is the frequency of XIN divided by 8. After reset is released, this mode is selected. (2) High-speed mode The internal clock is half the frequency of XIN. (3) Low-speed mode The internal clock is half the frequency of XCIN. (4) Low power dissipation mode The low power consumption operation can be realized by stopping the main clock XIN in low-speed mode. To stop the main clock, set bit 5 of the CPU mode register to "1". When the main clock XIN is restarted (by setting the main clock stop bit to "0"), set sufficient time for oscillation to stabilize. The sub-clock XCIN-XCOUT oscillating circuit can not directly input clocks that are generated externally. Accordingly, make sure to cause an external resonator to oscillate. Oscillation Control (2) Wait mode If the WIT instruction is executed, the internal clock stops at an "H" level, but the oscillator does not stop. The internal clock restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. To ensure that the interrupts will be received to release the STP or WIT state, their interrupt enable bits must be set to "1" before executing of the STP or WIT instruction. When releasing the STP state, the prescaler 12 and timer 1 will start counting the clock XIN divided by 16. Accordingly, set the timer 1 interrupt enable bit to "0" before executing the STP instruction. <Notes> * If you switch the mode between middle/high-speed and lowspeed, stabilize both XIN and XCIN oscillations. The sufficient time is required for the sub-clock to stabilize, especially immediately after power on and at returning from the stop mode. When switching the mode between middle/high-speed and low-speed, set the frequency on condition that f(XIN) > 3 x f(XCIN). * When using the oscillation stabilizing time set after STP instruction released bit set to "1", evaluate time to stabilize oscillation of the used oscillator and set the value to the timer 1 and prescaler 12. XCIN XCOUT (1) Stop mode If the STP instruction is executed, the internal clock stops at an "H" level, and X IN and X CIN oscillation stops. When the oscillation stabilizing time set after STP instruction released bit (bit 0 of address 003816) is "0", the prescaler 12 is set to "FF16" and timer 1 is set to "0116". When the oscillation stabilizing time set after STP instruction released bit is "1", set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and timer 1. After STP instruction is released, the input of the prescaler 12 is connected to count source which had set at executing the STP instruction, and the output of the prescaler 12 is connected to timer 1. Oscillator restarts when an external interrupt is received, but the internal clock is not supplied to the CPU (remains at "H") until timer 1 underflows. The internal clock is supplied for the first time, when timer 1 underflows. This ensures time for the clock oscillation using the ceramic resonators to be stabilized. When the oscillator is restarted by reset, apply "L" level to the RESET pin until the oscillation is stable since a wait time will not be generated. XIN Rd (Note) Rf Rd CCIN CCOUT CIN Fig 42. Ceramic resonator circuit XIN XCOUT Rf CCIN XOUT Open Rd External oscillation circuit CCOUT VCC VSS Fig 43. External clock input circuit Page 38 of 59 COUT Notes : Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. Also, if the oscillator manufacturer's data sheet specifies to add a feedback resistor externally to the chip though a feedback resistor exists on-chip, insert a feedback resistor between XIN and XOUT following the instruction. XCIN Rev.2.10 Nov 14, 2005 REJ03B0125-0210 XOUT 3850 Group (Spec.A QzROM version) [MISRG (MISRG)] 003816 MISRG consists of three control bits (bits 1 to 3) for middlespeed mode automatic switch and one control bit (bit 0) for oscillation stabilizing time set after STP instruction released. By setting the middle-speed mode automatic switch start bit to "1" while operating in the low-speed mode and setting the middle-speed mode automatic switch set bit to "1", X IN oscillation automatically starts and the mode is automatically switched to the middle-speed mode. b7 b0 MISRG (MISRG : address 003816) Oscillation stabilizing time set after STP instruction released bit 0: Automatically set "0116" to Timer 1, "FF16" to Prescaler 12 1: Automatically set nothing Middle-speed mode automatic switch set bit 0: Not set automatically 1: Automatic switching enable Middle-speed mode automatic switch wait time set bit 0: 6.5 to 7.5 machine cycles 1: 4.5 to 5.5 machine cycles Middle-speed mode automatic switch start bit (Depending on program) 0: Invalid 1: Automatic switch start Not used (return "0" when read) Note: When the mode is automatically switched from the low-speed mode to the middle-speed mode, the value of CPU mode register (address 003B16) changes. Fig 44. Structure of MISRG XCOUT XCIN "1" "0" Port XC switch bit XIN XOUT (Note 4) Timer 12 count source selection bit Main clock division ratio selection bits (Note 1) low-speed mode 1/4 1/2 Prescaler 12 1/2 High-speed or middle-speed mode Timer 1 (Note 3) Reset or STP instruction (Note 2) Main clock division ratio selection bits (Note 1) Middle-speed mode Timing (internal clock) High-speed or Low-speed mode Main clock stop bit Q S S R STP instruction WIT instruction R Q Reset Q S R STP instruction Reset Interrupt disable flag l Interrupt request Notes1: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register. When low-speed mode is selected, set port XC switch bit (b4) to "1". 2: f(XIN)/16 is supplied as the count source to the prescaler 12 at reset, the count source before executing the STP instruction is supplied as the count source at executing STP instruction. 3: When bit 0 of MISRG = "0", the prescaler 12 is set to "FF16" and timer 1 is set to "0116". When bit 0 of MISRG = "1", set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and timer 1. 4: Although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions. Fig 45. System clock generating circuit block diagram (Single-chip mode) Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 39 of 59 3850 Group (Spec.A QzROM version) Reset "0 C "0 M 4 C M " "1 6 " 1" " "0 " " C M " 0" "1 M 6 " C " "1 Middle-speed mode (f() = 1 MHz) CM7=0 CM6=1 CM5=0 (8 MHz oscillating) CM4=1 (32 kHz oscillating) CM 4 "1""0" 4 High-speed mode (f() = 4 MHz) CM7=0 CM6=0 CM5=0 (8 MHz oscillating) CM4=0 (32 kHz stopped) CM6 "1""0" High-speed mode (f() = 4 MHz) CM7=0 CM6=0 CM5=0 (8 MHz oscillating) CM4=1 (32 kHz oscillating) CM6 "1""0" "1 Middle-speed mode automatic switch set bit "1" C "0 M 7 C M " " 6 "0 "1 CM 7 "1""0" CM 4 "1""0" Middle-speed mode (f() = 1 MHz) CM7=0 CM6=1 CM5=0 (8 MHz oscillating) CM4=0 (32 kHz stopped) " " Low-speed mode (f() = 16 kHz) CM7=1 CM6=0 CM5=0 (8 MHz oscillating) CM4=1 (32 kHz oscillating) CM 5 "1""0" Middle-speed mode automatic switch start bit "1" Low-speed mode (f() = 16 kHz) CM7=1 CM6=0 CM5=1 (8 MHz stopped) CM4=1 (32 kHz oscillating) b7 b4 CPU mode register (CPUM : address 003B16) CM4 : Port XC switch bit 0 : I/O port function (stop oscillating) 1 : XCIN-XCOUT oscillating function CM5 : Main clock (XIN-XOUT) stop bit 0 : Operating 1 : Stopped CM7, CM6: Main clock division ratio selection bit b7 b6 0 0 : = f(XIN)/2 (High-speed mode) 0 1 : = f(XIN)/8 (Middle-speed mode) 1 0 : = f(XCIN)/2 (Low-speed mode) 1 1 : Not available Notes1: Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.) 2: The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3: Timer operates in the wait mode. 4: After STP instruction is released, the count source which had set by bit 2 (timer 12 count source selection bit) of the timer count source set register at executing the STP instruction is supplied to timer 1. Accordingly, when bit 0 of MISRG is "0" and the timer 12 count source selection bit is "0" (f(XIN)/16 or f(XCIN)/16), a delay of approximately 1 ms occurs automatically in the high/middle-speed mode. A delay of approximately 256 ms occurs automatically in the low-speed mode (at f(X IN) = 8 MHz, f(XCIN) = 32 kHz). When the timer 12 count source selection bit is "1" (f(X CIN)), a delay of approximately 16 ms occurs regardless of the operation mode. 5: Wait until oscillation stabilizes after oscillating the main clock X IN before the switching from the low-speed mode to middle/high-speed mode. 6: When the mode is switched to the middle-speed mode by the middle-speed mode automatic switch set bit of MISRG, the waiting time set by the middle-speed mode automatic switch wait time set bit is automatically generated, and then the mode is switched to the middle-speed mode. 7: The example assumes that 8 MHz is being applied to the X IN pin and 32 kHz to the X CIN pin. indicates the internal clock. Fig 46. State transitions of system clock Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 40 of 59 3850 Group (Spec.A QzROM version) NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is "1". After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. Interrupts The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction. Decimal Calculations * To calculate in decimal notation, set the decimal mode flag (D) to "1", then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. * In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. Timers If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1). Multiplication and Division Instructions * The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. * The execution of these instructions does not change the contents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used: * The data transfer instruction (LDA, etc.) * The operation instruction when the index X mode flag (T) is "1" * The addressing mode which uses the value of a direction register as an index * The bit-test instruction (BBC or BBS, etc.) to a direction register * The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direction registers. Serial Interface In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the S RDY1 signal, set the transmit enable bit, the receive enable bit, and the SRDY1 output enable bit to "1". Serial I/O1 continues to output the final bit from the TXD pin after transmission is completed. S OU T2 pin for serial I/O2 goes to high impedance after transmission is completed. When an external clock is used as synchronous clock in serial I/O1 or serial I/O2, write transmission data to the transmit buffer register or serial I/O2 register while the transfer clock is "H". Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 41 of 59 A/D Converter The comparator uses capacitive coupling amplifier whose charge will be lost if the clock frequency is too low. Therefore, make sure that f(XIN) in the middle/high-speed mode is at least on 500 kHz during an A/D conversion. Do not execute the STP instruction during an A/D conversion. Instruction Execution Time The instruction execution time is obtained by multiplying the frequency of the internal clock by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock is half of the XIN frequency in high-speed mode. Reserved Area, Reserved Bit Do not write any data to the reserved area in the SFR area and the special page. (Do not change the contents after reset.) AD Input Selection Register Be sure to fix bits 5 and 7 of the AD input selection register (address 003716) to "0". CPU Mode Register Be sure to fix bit 3 of the CPU mode register (address 003B16) to "1". Interrupt Request Register 1 Be sure to fix bits 1and 5 of the Interrupt request register 1 (address 003C16) to "0". 3850 Group (Spec.A QzROM version) NOTES ON USAGE Termination of Unused Pins. Be sure to perform the termination of unused pins. Handling of Source Pins In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (VCC pin) and GND pin (VSS pin) and between power source pin (VCC pin) and analog power source input pin (AVSS pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 F - 0.1 F is recommended. Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the power source voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. Electric Characteristic Differences Between Flash Memory, Mask ROM and QzROM Version MCUs There are differences in the manufacturing processes and the mask pattern among flash memory, mask ROM, and QzROM version MCUs due to the differences of the ROM type. Even when the ROM type is the same, when the memory size is different, the manufacturing processes and the mask pattern differ. For these reasons, the oscillation circuit constants and the characteristics such as a characteristic value, operation margin, noise immunity, and noise radiation within the limits of electrical characteristics may differ. When manufacturing an application system, please perform sufficient evaluations in each product. Especially, when switching a product (example: change from the mask ROM version to QzROM version), please perform sufficient evaluations by the switching product in the stage before massproducing an application system. Product Shipped in Blank As for the product shipped in blank, Renesas does not perform the writing test to user ROM area after the assembly process though the QzROM writing test is performed enough before the assembly process. Therefore, a writing error of approx.0.1 % may occur. Moreover, please note the contact of cables and foreign bodies on a socket, etc. because a writing environment may cause some writing errors. QzROM Version Connect the CNVSS /VPP pin the shortest possible to the GND pattern which is supplied to the VSS pin of the microcomputer. In addition connecting an approximately 5 k resistor in series to the GND could improve noise immunity. In this case as well as the above mention, connect the pin the shortest possible to the GND pattern which is supplied to the V S S pin of the microcomputer. * Reason The CNVSS/VPP pin is the power source input pin for the built-in QzROM. When programming in the QzROM, the impedance of the VPP pin is low to allow the electric current for writing to flow into the built-in QzROM. Because of this, noise can enter easily. If noise enters the VPP pin, abnormal instruction codes or data are read from the QzROM, which may cause a program runaway. Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 42 of 59 The shortest (Note) CNVSS/VPP Approx. 5k VSS (Note) The shortest Note. Shows the microcomputer's pin. Fig 47. Wiring for the CNVSS/VPP Notes On QzROM Writing Orders When ordering the QzROM product shipped after writing, submit the mask file (extension: .msk) which is made by the mask file converter MM. Be sure to set the ROM option ("MASK option" written in the mask file converter) setup when making the mask file by using the mask file converter MM. Notes On ROM Code Protect (QzROM product shipped after writing) As for the QzROM product shipped after writing, the ROM code protect is specified according to the ROM option setup data in the mask file which is submitted at ordering. Renesas Technology corp. uses the ROM option setup data at the ROM code protect address (address FFDB16) when writing to the QzROM. Consequently, the actual written value might differ from the ordered value as the contents of the ROM code protect address. The ROM option setup data in the mask file is "0016" for protect enabled or "FF16" for protect disabled. Therefore, the contents of the ROM code protect address of the QzROM product shipped after writing is "0016" or "FF16". Note that the mask file which has nothing at the ROM option data or has the data other than "0016" and "FF16" can not be accepted. DATA REQUIRED FOR QzROM WRITING ORDERS The following are necessary when ordering a QzROM product shipped after writing: 1. QzROM Writing Confirmation Form* 2. Mark Specification Form* 3. ROM data...........Mask file * For the QzROM writing confirmation form and the mark specification form, refer to the "Renesas Technology Corp." Homepage (http://www.renesas.com/homepage.jsp). Note that we cannot deal with special font marking (customer's trademark etc.) in QzROM microcomputer. 3850 Group (Spec.A QzROM version) ELECTRICAL CHARACTERISTICS Absolute maximum ratings Table 9 Symbol VCC VI Absolute maximum ratings VI VI Parameter Power source voltage Input voltage P00-P07, P10-P17, P20, P21, P24-P27, P30-P34, P40-P44, VREF Input voltage P22, P23 Input voltage RESET, XIN VI VO Input voltage Output voltage VO Pd Output voltage Power dissipation Topr Tstg Operating temperature Storage temperature Page 43 of 59 -0.3 to VCC + 0.3 -0.3 to 5.8 -0.3 to 8.0 -0.3 to VCC + 0.3 -0.3 to 5.8 Ta=25C 1. The rating becomes 300mW at the 42P2R-A/E package. Ratings -0.3 to 6.5 -0.3 to VCC + 0.3 CNVSS P00-P07, P10-P17, P20, P21, P24-P27, P30-P34, P40-P44, XOUT P22, P23 NOTES: Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Conditions All voltages are based on VSS. When an input voltage is measured, output transistors are cut off. 1000(1) -20 to 85 -40 to 125 Unit V V V V V V V mW C C 3850 Group (Spec.A QzROM version) Recommended operating conditions Table 10 Recommended operating conditions (1) (VCC = 1.8 to 5.5 V, Ta = -20 to 85 C, unless otherwise noted) Symbol VCC VSS VIH VIH Parameter Power source voltage(1) Power source voltage "H" input voltage P00-P07, P10-P17, P20, P21, P24-P27, P30-P34, P40-P44 "H" input voltage P22, P23 VIH "H" input voltage RESET, XIN VIH "H" input voltage CNVSS VIL "L" input voltage P00-P07, P10-P17, P20, P21, P24-P27, P30-P34, P40-P44 VIH "H" input voltage P22, P23 VIL "L" input voltage RESET VIL "L" input voltage XIN "L" input voltage CNVSS VIL f(XIN) Main clock input oscillation frequency(3) Conditions When start oscillating(2) High-speed mode f(XIN) 12.5 MHz f() = f(XIN)/2 f(XIN) 6.0 MHz f(XIN) 4.2 MHz f(XIN) 2.1 MHz f(XIN) 12.5 MHz Middle-speed mode f() = f(XIN)/8 f(XIN) 8.4 MHz f(XIN) 4.2 MHz f(XCIN) 50 kHz Low-speed mode f() = f(XCIN)/2 Limits Typ. 5.0 Max. 5.5 4.0 2.7 2.2 2.0 2.7 2.2 1.8 1.8 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 V V V V V V V V V V 0 Unit V 1.8 VCC < 2.7 V 0.85 VCC VCC 2.7 VCC < 5.5 V 0.8 VCC VCC 1.8 VCC < 2.7 V 2.7 VCC 5.5 V 1.8 VCC < 2.7 V 2.7 VCC 5.5 V 1.8 VCC < 2.7 V 2.7 VCC 5.5 V 1.8 VCC < 2.7 V 0.85 VCC 0.8 VCC 0.85 VCC 0.8 VCC 0.85 VCC 0.8 VCC 0 5.8 5.8 VCC VCC 8.0 8.0 0.16 VCC 2.7 VCC 5.5 V 0 0.2 VCC 1.8 VCC < 2.7 V 2.7 VCC 5.5 V 1.8 VCC < 2.7 V 2.7 VCC 5.5 V 1.8 VCC < 2.7 V 0 0 0 0 0 0.16 VCC 0.2 VCC 0.16 VCC 0.2 VCC 0.16 VCC V 1.8 VCC < 2.7 V 2.7 VCC 5.5 V 0 0 0.16 VCC 0.2 VCC 12.5 6.0 4.2 2.1 12.5 8.4 4.2 50 V High-speed mode f() = f(XIN)/2 Middle-speed mode f() = f(XIN)/8 f(XCIN) Min. 2.0 Sub-clock input oscillation frequency(3, 4) 4.0 VCC 5.5 V 2.7 VCC 5.5 V 2.2 VCC 5.5 V 2.0 VCC 5.5 V 2.7 VCC 5.5 V 2.2 VCC 5.5 V 1.8 VCC 5.5 V 32.768 V V V V V V MHz MHz MHz MHz MHz MHz MHz kHz NOTES: 1. When the A/D converter is used, refer to the recommended operating condition for A/D conversion. 2. The start voltage and the start time for oscillation depend on the using oscillator, oscillation circuit constant value and operating temperature range, etc.. Particularly a high-frequency oscillator might require some notes in the low voltage operation. 3. When the oscillation frequency has a duty cycle of 50%. 4. When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3. Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 44 of 59 3850 Group (Spec.A QzROM version) Table 11 Recommended operating conditions (2) (VCC = 1.8 to 5.5 V, Ta = -20 to 85 C, unless otherwise noted) Symbol Parameter Min. Limits Typ. Max. -10 Unit IOH(peak) "H" peak output current(1) IOL(peak) "L" peak output current(1) P00-P07, P10-P17, P20, P21, P24-P27, P30-P34, P40-P44 P00-P07, P20-P27, P30-P34, P40-P44 mA 10 mA IOL(peak) "L" peak output current(1) P10-P17 20 mA IOH(avg) "H" average output current(2) -5 mA IOL(avg) "L" average output current(2) P00-P07, P10-P17, P20, P21, P24-P27, P30-P34, P40-P44 P00-P07, P20-P27, P30-P34, P40-P44 5 mA IOL(avg) "L" average output current(2) P10-P17 15 mA IOH(peak) "H" total peak output current(3) P00-P07, P10-P17, P30-P34 -80 mA IOH(peak) "H" total peak output current(3) P20, P21, P24-P27, P40-P44, -80 mA IOL(peak) "L" total peak output current(3) P00-P07, P30-P34 80 mA IOL(peak) "L" total peak output current(3) P10-P17 120 mA IOL(peak) "L" total peak output current(3) P20-P27, P40-P44 80 mA IOH(peak) "H" total average output current(3) P00-P07, P10-P17, P30-P34 -40 mA IOH(peak) "H" total average output current(3) P20, P21, P24-P27, P40-P44 -40 mA IOL(avg) "L" total average output P00-P07, P30-P34 40 mA IOL(avg) "L" total average output current(3) P10-P17 60 mA IOL(avg) "L" total average output current(3) P20-P27, P40-P44 40 mA current(3) NOTES: 1. The peak output current is the peak current flowing in each port. 2. The average output current IOL(avg), IOH(avg) are average value measured over 100 ms. 3. The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 45 of 59 3850 Group (Spec.A QzROM version) Electrical characteristics Table 12 Electrical characteristics (1) (VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol VOH VOL VOL VT+ - VT- VT+ - VT- VT+ - VT- IIH IIH IIH IIL IIL IIL IIL VRAM Parameter "H" output voltage(1) P00-P07, P10-P17, P20, P21, P24-P27, P30-P34, P40-P44 "L" output voltage P00-P07, P20-P27, P30-P34, P40-P44 "L" output voltage P10-P17 Hysteresis CNTR0, CNTR1, INT0-INT3 Hysteresis RxD, SCLK1, SCLK2, SIN2 Hysteresis RESET "H" input current P00-P07, P10-P17, P20, P21, P24-P27, P30-P34, P40-P44 "H" input current RESET, CNVSS "H" input current XIN "L" input current P00-P07, P10-P17, P20-P27 P30-P34, P40-P44 "L" input current RESET, CNVSS "L" input current XIN "L" input current (at Pull-up) P00-P07, P10-P17, P20, P21, P24-P27, P30-P34, P40-P44 RAM hold voltage Test conditions IOH = -10 mA 4.0 VCC 5.5 V IOH = -1.0 mA 1.8 VCC 5.5 V IOL = 10 mA 4.0 VCC 5.5 V IOL = 1.0 mA 1.8 VCC 5.5 V IOL = 20 mA 4.0 VCC 5.5 V IOL = 10 mA 2.7 VCC 5.5 V IOL = 1.6 mA 1.8 VCC 5.5 V Min. VCC - 2.0 Limits Typ. Unit V VCC - 1.0 2.0 V 1.0 2.0 V 1.0 1.0 0.4 V 0.5 V 0.5 V VI = VCC Pin floating, Pull-up Transistor "off" VI = VCC VI = VCC 5.0 A 5.0 A A 4.0 VI = VSS Pin floating, Pull-up Transistor "off" VI = VSS -5.0 A -5.0 A -4.0 VI = VSS VI = VSS VCC = 5.0 V VI = VSS VCC = 3.0 V When clock stopped Max. A -25 -60 -120 A -8 -22 -40 A 1.8 V NOTES: 1. P25 is measured when the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 46 of 59 3850 Group (Spec.A QzROM version) Table 13 Electrical characteristics (2) (VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol ICC Parameter Test conditions Power source High-speed mode(1) current f(XIN) = 12.5 MHz f(XCIN) = 32.768 kHz f(XIN) = 8.0 MHz f(XCIN) = 32.768 kHz f(XIN) = 12.5 MHz (in WIT state) f(XCIN) = 32.768 kHz f(XIN) = 8.0 MHz (in WIT state) f(XCIN) = 32.768 kHz Middle-speed mode(1) f(XIN) = 12.5 MHz f(XCIN) = stopped f(XIN) =8.0 MHz f(XCIN) = stopped f(XIN) = 12.5 MHz (in WIT state) f(XCIN) = stopped f(XIN) = 8.0 MHz (in WIT state) f(XCIN) = stopped f(XIN) = stopped Low-speed mode f(XCIN) = 32.768 kHz (VCC = 5.0 V)(1) f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) f(XIN) = stopped Low-speed mode f(XCIN) = 32.768 kHz (VCC = 3.0 V)(1) f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Increment when A/D conversion is executed All oscillation stopped Ta = 25 C (in STP state)(1) Ta = 85 C NOTES: 1. Output transistors are cut off. Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 47 of 59 Min. Limits Typ. 6.0 Max. 13.0 4.3 10.0 mA 1.8 4.5 mA 1.4 4.2 mA 2.8 7.0 mA 2.0 6.5 mA 1.8 4.2 mA 1.3 4.0 mA 75 200 A 65 100 A 15 55 A 10 20 A 300 0.1 Unit mA A 1.0 10 A A 3850 Group (Spec.A QzROM version) A/D converter recommended operating conditions Table 14 A/D converter recommended operating conditions (VCC = 2.2 to 5.5 V, VSS = AVSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol VCC VREF AVSS VIA f(XIN) Parameter Power source voltage (When A/D converter is used) A/D convert reference voltage Analog power source voltage Analog input voltage AN0-AN8 Main clock input oscillation frequency (When A/D converter is used) Test conditions Min. 2.2 Limits Typ. 5.0 2.0 Max. 5.5 VCC Unit V High-speed mode f() = f(XIN)/2 4.0 VCC 5.5 V 2.7 VCC 5.5 V AVSS 0.5 0.5 VCC 12.5 6.0 V V V MHz MHz Middle-speed mode f() = f(XIN)/8 2.2 VCC 5.5 V 2.7 VCC 5.5 V 2.2 VCC 5.5 V 0.5 0.5 0.5 4.2 12.5 8.4 MHz MHz MHz 0 A/D converter characteristics Table 15 A/D converter characteristics (VCC = 2.2 to 5.5 V, VSS = AVSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol - - Parameter Resolution Absolute accuracy Test conditions 2.2 VCC < 2.7 V 2.7 VCC 5.5 V High-speed mode, Middle-speed mode Low-speed mode tCONV Conversion time RLADDER IVREF Ladder resistor Reference power source input current VREF = 5.0 V VREF "on" VREF = 5.0 V VREF "off" A/D port input current II(AD) Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Min. Page 48 of 59 50 Limits Typ. 40 35 150 0.5 Max. 10 5 4 61 200 5.0 5.0 Unit bit LSB LSB 2tc(XIN) s k A A A 3850 Group (Spec.A QzROM version) Timing Requirements Table 16 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Limits Typ. Symbol Parameter tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tWH(INT) tWL(INT) tC(SCLK1) Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0 to INT3 input "H" pulse width INT0 to INT3 input "L" pulse width Serial I/O1 clock input cycle time(1) Min. 20 80 32 32 200 80 80 80 80 800 tWH(SCLK1) Serial I/O1 clock input "H" pulse width(1) 370 Serial I/O1 clock input "L" pulse width(1) tsu(RxD-SCLK1) Serial I/O1 input setup time th(SCLK1-RxD) Serial I/O1 input hold time Serial I/O2 clock input cycle time tC(SCLK2) Serial I/O2 clock input "H" pulse width tWH(SCLK2) Serial I/O2 clock input "L" pulse width tWL(SCLK2) tsu(SIN2-SCLK2) Serial I/O2 clock input setup time th(SCLK2-SIN2) Serial I/O2 clock input hold time 370 ns 220 100 1000 400 400 200 200 ns ns ns ns ns ns ns tWL(SCLK1) Max. Unit XIN cycle ns ns ns ns ns ns ns ns ns ns NOTES: 1. When f(XIN) = 8 MHz and bit 6 of address 001A16 is "1" (clock synchronous). Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is "0" (UART). Table 17 Timing requirements (2) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Limits Typ. Symbol Parameter tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tWH(INT) tWL(INT) tC(SCLK1) Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0 to INT3 input "H" pulse width INT0 to INT3 input "L" pulse width Serial I/O1 clock input cycle time(1) Min. 20 166 66 66 500 230 230 230 230 2000 tWH(SCLK1) Serial I/O1 clock input "H" pulse width(1) 950 ns tWL(SCLK1) width(1) 950 ns 400 200 2000 950 950 400 300 ns ns ns ns ns ns ns Serial I/O1 clock input "L" pulse tsu(RxD-SCLK1) Serial I/O1 input setup time th(SCLK1-RxD) Serial I/O1 input hold time Serial I/O2 clock input cycle time tC(SCLK2) Serial I/O2 clock input "H" pulse width tWH(SCLK2) Serial I/O2 clock input "L" pulse width tWL(SCLK2) tsu(SIN2-SCLK2) Serial I/O2 clock input setup time th(SCLK2-SIN2) Serial I/O2 clock input hold time NOTES: 1. When f(XIN) = 4 MHz and bit 6 of address 001A16 is "1" (clock synchronous). Divide this value by four when f(XIN) = 4 MHz and bit 6 of address 001A16 is "0" (UART). Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 49 of 59 Max. Unit XIN cycle ns ns ns ns ns ns ns ns ns 3850 Group (Spec.A QzROM version) Switching characteristics Table 18 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol Parameter Test conditions Fig. 48 Min. tC(SCLK1)/2-30 Limits Typ. Max. tWH(SCLK1) Serial I/O1 clock output "H" pulse width tWL(SCLK1) Serial I/O1 clock output "L" pulse width td(SCLK1-TXD) Serial I/O1 output delay time(1) tV(SCLK1-TXD) Serial I/O1 output valid time(1) tr(SCLK1) Serial I/O1 clock output rising time 30 tf(SCLK1) Serial I/O1 clock output falling time 30 -30 Serial I/O2 clock output "H" pulse width tWL(SCLK2) Serial I/O2 clock output "L" pulse width tC(SCLK2)/2-160 Serial I/O2 output delay time(2) tV(SCLK2-SOUT2) Serial I/O2 output valid time(2) ns 140 tC(SCLK2)/2-160 td(SCLK2-SOUT2) ns tC(SCLK1)/2-30 tWH(SCLK2) Unit ns ns ns ns ns ns 200 ns 30 ns 0 ns tf(SCLK2) Serial I/O2 clock output falling time tr(CMOS) CMOS output rising time(3) 10 30 ns tf(CMOS) CMOS output falling time(3) 10 30 ns NOTES: 1. When the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2. When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register 1 (bit 7 of address 001516) is "0". 3. The XOUT pin is excluded. Table 19 Switching characteristics (2) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol Parameter tWH(SCLK1) Serial I/O1 clock output "H" pulse width tWL(SCLK1) Serial I/O1 clock output "L" pulse width td(SCLK1-TXD) Serial I/O1 output delay Test conditions Fig. 48 Min. tC(SCLK1)/2-50 Limits Typ. Max. ns tC(SCLK1)/2-50 ns 350 time(1) -30 tV(SCLK1-TXD) Serial I/O1 output valid time(1) tr(SCLK1) Serial I/O1 clock output rising time 50 Serial I/O1 clock output falling time 50 tf(SCLK1) tWH(SCLK2) Serial I/O2 clock output "H" pulse width tC(SCLK2)/2-240 tWL(SCLK2) Serial I/O2 clock output "L" pulse width tC(SCLK2)/2-240 td(SCLK2-SOUT2) Serial I/O2 output delay time(2) tV(SCLK2-SOUT2) Serial I/O2 output valid time(2) Unit ns ns ns ns ns ns 400 0 ns ns tf(SCLK2) Serial I/O2 clock output falling time 50 ns tr(CMOS) CMOS output rising time(3) 20 50 ns tf(CMOS) CMOS output falling time(3) 20 50 ns NOTES: 1. When the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2. When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register 1 (bit 7 of address 001516) is "0". 3. The XOUT pin is excluded. Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 50 of 59 3850 Group (Spec.A QzROM version) Measurement output pin 100pF CMOS output Fig 48. Circuit for measuring output switching characteristics Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 51 of 59 3850 Group (Spec.A QzROM version) tC(CNTR) tWL(CNTR) tWH(CNTR) 0.8VCC CNTR0 CNTR1 0.2VCC tWH(INT) INT0 to INT3 tWL(INT) 0.8VCC 0.2VCC tW(RESET) RESET 0.8VCC 0.2VCC tC(XIN) tWL(XIN) tWH(XIN) 0.8VCC XIN 0.2VCC tC(SCLK1), tC(SCLK2) SCLK1 SCLK2 tf tWL(SCLK1), tWL(SCLK2) tf 0.8VCC 0.2VCC tsu(RXD-SCLK1), tsu(SIN2-SCLK2) RXD SIN2 th(SCLK1-RXD), th(SCLK2-SIN2) 0.8VCC 0.2VCC td(SCLK1-TXD), td(SCLK2-SOUT2) TXD SOUT2 Fig 49. Timing diagram Rev.2.10 Nov 14, 2005 REJ03B0125-0210 tWH(SCLK1), tWH(SCLK2) Page 52 of 59 tv(SCLK1-TXD), tv(SCLK2-SOUT2) 3850 Group (Spec.A QzROM version) PACKAGE OUTLINE RENESAS Code PRDP0042BA-A Previous Code 42P4B MASS[Typ.] 4.1g 22 1 21 *1 E 42 e1 JEITA Package Code P-SDIP42-13x36.72-1.78 c D A A2 *2 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. Reference Symbol *3 e JEITA Package Code P-SSOP42-8.4x17.5-0.80 RENESAS Code PRSP0042GA-B *3 bp b3 Previous Code 42P2R-E b2 MASS[Typ.] 0.6g 22 *1 E 42 HE Min Nom Max e1 14.94 15.24 15.54 D 36.5 36.7 36.9 E 12.85 13.0 13.15 A 5.5 A1 0.51 A2 3.8 bp 0.35 0.45 0.55 b2 0.63 0.73 1.03 b3 0.9 1.0 1.3 c 0.22 0.27 0.34 15 0 e 1.528 1.778 2.028 L 3.0 A1 L SEATING PLANE Dimension in Millimeters F NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 21 1 Index mark A2 A1 c *2 Reference Symbol L A D e y *3 b p Detail F D E A2 A A1 bp c HE e y L Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 53 of 59 Dimension in Millimeters Min Nom Max 17.3 17.5 17.7 8.2 8.4 8.6 2.0 2.4 0.05 0.25 0.3 0.4 0.13 0.15 0.2 10 0 11.63 11.93 12.23 0.65 0.8 0.95 0.15 0.3 0.5 0.7 PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. 3850 Group (Spec.A QzROM version) APPENDIX NOTES ON PROGRAMMING Set D flag to "1" 1. Processor Status Register (1) Initializing of processor status register Flags which affect program execution must be initialized after a reset. In particular, it is essential to initialize the T and D flags because they have an important effect on calculations. <Reason> After a reset, the contents of the processor status register (PS) are undefined except for the I flag which is "1". ADC or SBC instruction NOP instruction SEC, CLC, or CLD instruction Reset Initializing of flags Fig 3. Execution of decimal calculations 4. JMP instruction When using the JMP instruction in indirect addressing mode, do not specify the last address on a page as an indirect address. Main program Fig 1. Initialization of processor status register (2) How to reference the processor status register To reference the contents of the processor status register (PS), execute the PHP instruction once then read the contents of (S+1). If necessary, execute the PLP instruction to return the PS to its original status. (S) (S) + 1 Fig 2. Stored PS Stack memory contents after PHP instruction execution 2. BRK instruction (1) Interrupt priority level When the BRK instruction is executed with the following conditions satisfied, the interrupt execution is started from the address of interrupt vector which has the highest priority. * Interrupt request bit and interrupt enable bit are set to "1". * Interrupt disable flag (I) is set to "1" to disable interrupt. 3. Decimal calculations (1) Execution of decimal calculations The ADC and SBC are the only instructions which will yield proper decimal notation, set the decimal mode flag (D) to "1" with the SED instruction. After executing the ADC or SBC instruction, execute another instruction before executing the SEC, CLC, or CLD instruction. (2) Notes on status flag in decimal mode When decimal mode is selected, the values of three of the flags in the status register (the N, V, and Z flags) are invalid after a ADC or SBC instruction is executed. The carry flag (C) is set to "1" if a carry is generated as a result of the calculation, or is cleared to "0" if a borrow is generated. To determine whether a calculation has generated a carry, the C flag must be initialized to "0" before each calculation. To check for a borrow, the C flag must be initialized to "1" before each calculation. Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 54 of 59 5. Multiplication and Division Instructions * The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. * The execution of these instructions does not change the contents of the processor status register. 6. Ports The contents of the port direction registers cannot be read. The following cannot be used: * The data transfer instruction (LDA, etc.) * The operation instruction when the index X mode flag (T) is "1" * The addressing mode which uses the value of a direction register as an index * The bit-test instruction (BBC or BBS, etc.) to a direction register * The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direction registers. 7. Instruction Execution Time The instruction execution time can be obtained by multiplying the frequency of the internal clock by the number of cycles mentioned in the 740 Family Software Manual. The frequency of the internal clock is the twice the XIN cycle in high-speed mode, 8 times the XIN cycle in middle-speed mode, and the twice the XCIN in low-speed mode. 8. Reserved Area, Reserved Bit Do not write any data to the reserved area in the SFR area and the special page. (Do not change the contents after reset.) 9. CPU Mode Register Be sure to fix bit 3 of the CPU mode register (address 003B16) to "1". PRELIMINARY 3850 Group (Spec.A QzROM version) NOTES ON PERIPHERAL FUNCTIONS Notes on Input and Output Ports 1. Notes in standby state In standby state *1 , do not make input levels of an I/O port "undefined", especially for I/O ports of the N-channel opendrain. When setting the N-channel open-drain port as an output, do not make input levels of an I/O port "undefined", too. Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a resistor. When determining a resistance value, note the following points: * External circuit * Variation of output levels during the ordinary operation <Reason> When setting as an input port with its direction register, the transistor becomes the OFF state, which causes the ports to be the high-impedance state. Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of an I/O port are "undefined". This may cause power source current. In I/O ports of N-channel open-drain, when the contents of the port latch are "1", even if it is set as an output port with its direction register, it becomes the same phenomenon as the case of an input port. NOTES: 1. Standby state : stop mode by executing STP instruction wait mode by executing WIT instruction 2. Modifying output data with bit managing instruction When the port latch of an I/O port is modified with the bit managing instruction*2, the value of the unspecified bit may be changed. <Reason> The bit managing instructions are read-modify-write form instructions for reading and writing data by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an I/O port, the following is executed to all bits of the port latch. * As for bit which is set for input port: The pin state is read in the CPU, and is written to this bit after bit managing. * As for bit which is set for output port: The bit value is read in the CPU, and is written to this bit after bit managing. Note the following: * Even when a port which is set as an output port is changed for an input port, its port latch holds the output data. * As for a bit of which is set for an input port, its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its port latch contents. NOTES: 2. Bit managing instructions : SEB and CLB instructions Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 55 of 59 Notice: This is not a final specification. Some parametric limits are subject to change. Termination of Unused Pins 1. Terminate unused pins (1) I/O ports : * Set the I/O ports for the input mode and connect them to VCC or V SS through each resistor of 1 k to 10 k. In the port which can select a internal pull-up resistor, the internal pull-up resistor can be used. Set the I/O ports for the output mode and open them at "L" or "H". * When opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. Thus, the potential at these pins is undefined and the power source current may increase in the input mode. With regard to an effects on the system, thoroughly perform system evaluation on the user side. * Since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. (2) The AVSS pin when not using the A/D converter : * When not using the A/D converter, handle a power source pin for the A/D converter, AVSS pin as follows: AVSS: Connect to the VSS pin. 2. Termination remarks (1) Input ports and I/O ports : Do not open in the input mode. <Reason> * The power source current may increase depending on the firststage circuit. * An effect due to noise may be easily produced as compared with proper termination (1) in 1 shown on the above. (2) I/O ports : When setting for the input mode, do not connect to VCC or VSS directly. <Reason> If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between a port and VCC (or VSS). (3) I/O ports : When setting for the input mode, do not connect multiple ports in a lump to VCC or VSS through a resistor. <Reason> If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between ports. * At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less) from microcomputer pins. PRELIMINARY 3850 Group (Spec.A QzROM version) Notes on Interrupts 1. Change of relevant register settings When the setting of the following registers or bits is changed, the interrupt request bit may be set to "1". When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. * Interrupt edge selection register (address 3A16) * Timer XY mode register (address 2316) Set the above listed registers or bits as the following sequence. Set the corresponding interrupt enable bit to "0" (disabled). Notice: This is not a final specification. Some parametric limits are subject to change. 3. Interrupt Request Register 1 Be sure to fix bits 1and 5 of the Interrupt request register 1 (address 003C16) to "0". Notes on Timer * If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1). * When switching the count source by the timer 12, X and Y count source selection bits, the value of timer count is altered in unconsiderable amount owing to generating of thin pulses in the count input signals. Therefore, select the timer count source before set the value to the prescaler and the timer. Set the interrupt edge select bit (active edge switch bit) or the interrupt (source) select bit to "1". Notes on Serial Interface NOP (one or more instructions) Set the corresponding interrupt request bit to "0" (no interrupt request issued). Set the corresponding interrupt enable bit to "1" (enabled). Fig 4. Sequence of changing relevant register <Reason> When setting the followings, the interrupt request bit may be set to "1". * When setting external interrupt active edge Concerned register:Interrupt edge selection register (address 3A16) Timer XY mode register (address 2316) * When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated. Concerned register: Interrupt edge selection register (address 3A16) 2. Check of interrupt request bit When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request register immediately after this bit is set to "0" by using a data transfer instruction, execute one or more instructions before executing the BBC or BBS instruction. Clear the interrupt request bit to "0" (no interrupt issued) NOP (one or more instructions) Execute the BBC or BBS instruction * Data transfer instruction: LDM, LDA, STA, STX, and STY instructions Fig 5. Sequence of check of interrupt request bit <Reason> If the BBC or BBS instruction is executed immediately after an interrupt request bit of an interrupt request register is cleared to "0", the value of the interrupt request bit before being cleared to "0" is read. Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 56 of 59 1. Notes when selecting clock synchronous serial I/O (Serial I/O1) (1) Stop of transmission operation Clear the serial I/O1 enable bit and the transmit enable bit to "0" (Serial I/O1 and transmit disabled). <Reason> Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O1 enable bit is cleared to "0" (Serial I/O1 disabled), the internal transmission is running (in this case, since pins TxD, RxD, SCLK1, and SRDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O1 enable bit is set to "1" at this time, the data during internally shifting is output to the TxD pin and an operation failure occurs. (2) Stop of receive operation Clear the receive enable bit to "0" (receive disabled), or clear the serial I/O1 enable bit to "0" (Serial I/O1 disabled). (3) Stop of transmit/receive operation Clear the transmit enable bit and receive enable bit to "0" simultaneously (transmit and receive disabled). (when data is transmitted and received in the clock synchronous serial I/O mode, any one of data transmission and reception cannot be stopped.) <Reason> In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of transmission and reception is disabled, a bit error occurs because transmission and reception cannot be synchronized. In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to "0" (transmit disabled). Also, the transmission circuit is not initialized by clearing the serial I/O1 enable bit to "0" (Serial I/O1 disabled) (refer to (1) in 1). (4) SRDY1 output of reception side (Serial I/O1) When signals are output from the SRDY1 pin on the reception side by using an external clock in the clock synchronous serial I/O mode, set all of the receive enable bit, the SRDY1 output enable bit, and the transmit enable bit to "1" (transmit enabled). PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. 3850 Group (Spec.A QzROM version) 2. Notes when selecting clock asynchronous serial I/O (Serial I/O1) (1) Stop of transmission operation Clear the transmit enable bit to "0" (transmit disabled). <Reason> Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O1 enable bit is cleared to "0" (Serial I/O1 disabled), the internal transmission is running (in this case, since pins TxD, RxD, SCLK1, and SRDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O1 enable bit is set to "1" at this time, the data during internally shifting is output to the TxD pin and an operation failure occurs. (2) Stop of receive operation Clear the receive enable bit to "0" (receive disabled). (3) Stop of transmit/receive operation Only transmission operation is stopped. Clear the transmit enable bit to "0" (transmit disabled). <Reason> Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/O1 enable bit is cleared to "0" (Serial I/O1 disabled), the internal transmission is running (in this case, since pins TxD, RxD, SCLK1, and SRDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/O1 enable bit is set to "1" at this time, the data during internally shifting is output to the TxD pin and an operation failure occurs. Only receive operation is stopped. Clear the receive enable bit to "0" (receive disabled). 3. Setting serial I/O1 control register again (Serial I/O1) Set the serial I/O1 control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to "0". Clear both the transmit enable bit (TE) and the receive enable bit (RE) to "0" Fig 6. Can be set with the LDM instruction at the same time Sequence of setting serial I/O1 control register again 4. Data transmission control with referring to transmit shift register completion flag (Serial I/O1) The transmit shift register completion flag changes from "1" to "0" with a delay of 0.5 to 1.5 shift clocks. When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. Rev.2.10 Nov 14, 2005 REJ03B0125-0210 (1) Set the interrupt enable bit to "0" (disabled) with CLB instruction. (2) Prepare serial I/O for transmission/reception.. (3) Set the interrupt request bit to "0" with CLB instruction after 1 or more instruction has been executed. (4) Set the interrupt enable bit to "1" (enabled). <Reason> When the transmission enable bit is set to "1", the transmit buffer empty flag and transmit shift register completion flag are set to "1". The interrupt request is generated and the transmission interrupt request bit is set regardless of which of the two timings listed below is selected as the timing for the transmission interrupt to be generated. * Transmit buffer empty flag is set to "1" * Transmit shift register completion flag is set to "1" 6. Transmission control when external clock is selected (Serial I/O1 clock synchronous mode) When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to "1" at "H" of the SCLK1 input level. Also, write the transmit data to the transmit buffer register (serial I/O shift register) at "H" of the SCLK1 input level. 7. Transmit data writing (Serial I/O2) In the clock synchronous serial I/O, when selecting an external clock as synchronous clock, write the transmit data to the serial I/O2 register (serial I/O shift register) at "H" of the transfer clock input level. Notes on PWM The PWM starts after the PWM enable bit is set to enable and "L" level is output from the PWM pin. The length of this "L" level output is as follows: Set the bits 0 to 3 and bit 6 of the serial I/O1 control register Set both the transmit enable bit (TE) and the receive enable bit (RE), or one of them to "1" 5. Transmit interrupt request when transmit enable bit is set (SerialI/O1) When the transmit interrupt is used, set the transmit interrupt enable bit to transmit enabled as shown in the following sequence. Page 57 of 59 n+1 2 * f(XIN) (s) (Count source selection bit = "0", where n is the value set in the prescaler) n+1 f(XIN) (s) (Count source selection bit = "1", where n is the value set in the prescaler) PRELIMINARY 3850 Group (Spec.A QzROM version) Notes on A/D Converter 1. Analog input pin Make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0.01 F to 1 F. Further, be sure to verify the operation of application products on the user side. <Reason> An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when signals from signal source with high impedance are input to an analog input pin, charge and discharge noise generates. This may cause the A/D conversion precision to be worse. 2. A/D converter power source pin The AVSS pin is A/D converter power source pin. Regardless of using the A/D conversion function or not, connect it as following : * AVSS : Connect to the VSS line <Reason> If the AVSS pin is opened, the microcomputer may have a failure because of noise or others. 3. Clock frequency during A/D conversion The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock frequency is too low. Thus, make sure the following during an A/D conversion. * f(XIN) is 500 kHz or more in middle-/high-speed mode. * Do not execute the STP instruction. * When the A/D converter is operated at low-speed mode, f(XIN) do not have the lower limit of frequency, because of the A/D converter has a built-in self-oscillation circuit. 4. AD Input Selection Register Be sure to fix bits 5 and 7 of the AD input selection register (address 003716) to "0". Notes on Watchdog Timer * Make sure that the watchdog timer does not underflow while waiting Stop release, because the watchdog timer keeps counting during that term. * When the STP instruction disable bit has been set to "1", it is impossible to switch it to "0" by a program. Notice: This is not a final specification. Some parametric limits are subject to change. 2. Reset release after power on When releasing the reset after power on, such as power-on reset, release reset after XIN passes more than 20 cycles in the state where the power supply voltage is 1.8 V or more and the XIN oscillation is stable. <Reason> To release reset, the RESET pin must be held at an "L" level for 20 cycles or more of XIN in the state where the power source voltage is between 1.8 V and 5.5 V, and XIN oscillation is stable. Notes on Using Stop Mode 1. Register setting Since values of the prescaler 12 and Timer 1 are automatically reloaded when returning from the stop mode, set them again, respectively. (When the oscillation stabilizing time set after STP instruction released bit is "0") When using the oscillation stabilizing time set after STP instruction released bit set to "1", evaluate time to stabilize oscillation of the used oscillator and set the value to the timer 1 and prescaler 12. 2. Clock restoration After restoration from the stop mode to the normal mode by an interrupt request, the contents of the CPU mode register previous to the STP instruction execution are retained. Accordingly, if both main clock and sub clock were oscillating before execution of the STP instruction, the oscillation of both clocks is resumed at restoration. In the above case, when the main clock side is set as a system clock, the oscillation stabilizing time for approximately 8,000 cycles of the XIN input is reserved at restoration from the stop mode. At this time, note that the oscillation on the sub clock side may not be stabilized even after the lapse of the oscillation stabilizing time of the main clock side. Notes on Wait Mode * Clock restoration If the wait mode is released by a reset when XCIN is set as the system clock and XIN oscillation is stopped during execution of the WIT instruction, XCIN oscillation stops, X IN oscillations starts, and XIN is set as the system clock. In the above case, the RESET pin should be held at "L" until the oscillation is stabilized. Notes on RESET Pin 1. Connecting capacitor In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the RESET pin and the VSS pin. Use a 1000 pF or more capacitor for high frequency use. When connecting the capacitor, note the following : * Make the length of the wiring which is connected to a capacitor as short as possible. * Be sure to verify the operation of application products on the user side. <Reason> If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may cause a microcomputer failure. Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 58 of 59 Notes on Restarting Oscillation * Restarting oscillation Usually, when the MCU stops the clock oscillation by STP instruction and the STP instruction has been released by an external interrupt source, the fixed values of Timer 1 and Prescaler 12 (Timer 1 = "0116 ", Prescaler 12 = "FF 16 ") are automatically reloaded in order for the oscillation to stabilize. The user can inhibit the automatic setting by writing "1" to bit 0 of MISRG (address 003816). However, by setting this bit to "1", the previous values, set just before the STP instruction was executed, will remain in Timer 1 and Prescaler 12. Therefore, you will need to set an appropriate value to each register, in accordance with the oscillation stabilizing time, before executing the STP instruction. <Reason> Oscillation will restart when an external interrupt is received. However, internal clock is supplied to the CPU only when Timer 1 starts to underflow. This ensures time for the clock oscillation using the ceramic resonators to be stabilized. PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. 3850 Group (Spec.A QzROM version) Handling of Source Pins In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (VCC pin) and GND pin (VSS pin) and between power source pin (VCC pin) and analog power source input pin (AVSS pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 F-0.1 F is recommended. The shortest (Note) CNVSS/VPP Approx. 5k VSS (Note) Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the power source voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. Electric Characteristic Differences Between Flash Memory, Mask ROM and QzROM Version MCUs There are differences in the manufacturing processes and the mask pattern among flash memory, mask ROM, and QzROM version MCUs due to the differences of the ROM type. Even when the ROM type is the same, when the memory size is different, the manufacturing processes and the mask pattern differ. For these reasons, the oscillation circuit constants and the characteristics such as a characteristic value, operation margin, noise immunity, and noise radiation within the limits of electrical characteristics may differ. When manufacturing an application system, please perform sufficient evaluations in each product. Especially, when switching a product (example: change from the mask ROM version to QzROM version), please perform sufficient evaluations by the switching product in the stage before massproducing an application system. Product Shipped in Blank As for the product shipped in blank, Renesas does not perform the writing test to user ROM area after the assembly process though the QzROM writing test is performed enough before the assembly process. Therefore, a writing error of approx.0.1 % may occur. Moreover, please note the contact of cables and foreign bodies on a socket, etc. because a writing environment may cause some writing errors. QzROM Version Connect the CNVSS /VPP pin the shortest possible to the GND pattern which is supplied to the VSS pin of the microcomputer. In addition connecting an approximately 5 k resistor in series to the GND could improve noise immunity. In this case as well as the above mention, connect the pin the shortest possible to the GND pattern which is supplied to the V S S pin of the microcomputer. * Reason The CNVSS/VPP pin is the power source input pin for the built-in QzROM. When programming in the QzROM, the impedance of the VPP pin is low to allow the electric current for writing to flow into the built-in QzROM. Because of this, noise can enter easily. If noise enters the VPP pin, abnormal instruction codes or data are read from the QzROM, which may cause a program runaway. Rev.2.10 Nov 14, 2005 REJ03B0125-0210 Page 59 of 59 The shortest Note. Shows the microcomputer's pin. Fig 7. Wiring for the CNVSS/VPP Notes On QzROM Writing Orders When ordering the QzROM product shipped after writing, submit the mask file (extension: .mask) which is made by the mask file converter MM. Be sure to set the ROM option ("MASK option" written in the mask file converter) setup when making the mask file by using the mask file converter MM. Notes On ROM Code Protect (QzROM product shipped after writing) As for the QzROM product shipped after writing, the ROM code protect is specified according to the ROM option setup data in the mask file which is submitted at ordering. Renesas Technology corp. uses the ROM option setup data at the ROM code protect address (address FFDB16) when writing to the QzROM. Consequently, the actual written value might differ from the ordered value as the contents of the ROM code protect address. The ROM option setup data in the mask file is "0016" for protect enabled or "FF16" for protect disabled. Therefore, the contents of the ROM code protect address of the QzROM product shipped after writing is "0016" or "FF16". Note that the mask file which has nothing at the ROM option data or has the data other than "0016" and "FF16" can not be accepted. DATA REQUIRED FOR QzROM WRITING ORDERS The following are necessary when ordering a QzROM product shipped after writing: 1. QzROM Writing Confirmation Form* 2. Mark Specification Form* 3. ROM data...........Mask file * For the QzROM writing confirmation form and the mark specification form, refer to the "Renesas Technology Corp." Homepage (http://www.renesas.com/homepage.jsp). Note that we cannot deal with special font marking (customer's trademark etc.) in QzROM microcomputer. REVISION HISTORY Rev. Date 1.00 Dec. 10, 2004 3850 Group (Spec.A QzROM version) Data Sheet Description Page - Summary First edition issued <Updating from Shortsheet (REJ03B0123-0100Z; Rev.1.00> 1 * Power source voltage is revised. * Power dissipation is partly revised. APPLICATION is partly deleted. 2.00 Sep. 09, 2005 5 Table 2 is partly added. Note of Table 2 is added. - Delete the following: "PRELIMINARY" 1, 4-6 Package name of 42P4B is revised. 42P4B PRDP0042BA-A 3 Table 1 is partly revised. 4 Fig.3 is partly revised. 6 Table 4 is partly revised. Notes on differences among 3850 group (standard), 3850 group (spec.H), and 3850 group (spec.A) is partly revised. 11 * ROM Code Protect Address (address FFDB16) is added. Fig.8 is partly revised. 12 Fig.9 is partly revised. 13 Table 7 is partly revised. 16 Fig.12 is partly revised. 35 WATCHDOG TIMER is revised. Fig.38 is partly revised. 38 Oscillation Control (1) Stop mode is partly revised. 41 Reserved Area is revised. Reserved Area Reserved Area, Reserved bit 42 The followings are added; - Termination of Unused Pins - QzROM Version - Notes On QzROM Writing Orders - Notes On ROM Code Protect - DATA REQUIRED FOR QzROM WRITING ORDERS Flash Memory Version / QzROM Version is deleted. 2.01 2.10 Oct. 13, 2005 Nov. 14, 2005 43 Table 9 is partly revised. 53 PACKAGE OUTLINE of 42P4B is revised. 5 Note 1 of Table 2 is partly revised. 11 * ROM Code Protect Address (address FFDB16) is partly revised. 42 Notes On QzROM Writing Orders, Notes On ROM Code Protect are partly revised. 35 Fig 37. Block diagram of Watchdog timer; STP instruction disable bit STP instruction function selection bit revised 42 QzROM version; approximately 1 k to 5 k resistor approximately 5 k resistor Fig 47. Wiring for the CNVSS/VPP added Notes On QzROM Writing Orders; (extension: .mask) (extension: .msk) revised 53 Package Outline revised 54-59 Appendix added (1/1) Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> 2-796-3115, Fax: <82> 2-796-2145 Renesas Technology Malaysia Sdn. Bhd. Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 (c) 2005. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .4.0